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2010 – 2019
- 2016
[c2]R. Berthelon, François Andrieu, P. Perreau, E. Baylac, A. Pofelski, Emmanuel Josse, Didier Dutartre, A. Claverie, Michel Haond:
Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration. ESSDERC 2016: 127-130- 2014
- [c1]François Andrieu, Mikaël Cassé, E. Baylac, P. Perreau, O. Nier, Denis Rideau, R. Berthelon, Franck Pourchon, A. Pofelski, Barbara De Salvo, C. Gallon, Vincent Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, Vincent Barral, Rossella Ranica, Nicolas Planes, Walter Schwarzenbach, E. Richard, Emmanuel Josse, Olivier Weber, Franck Arnaud, Maud Vinet, Olivier Faynot
, Michel Haond:
Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs. ESSDERC 2014: 106-109
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