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2020 – today
- 2024
[j33]Ankit Wagle, Gian Singh
, Sunil P. Khatri, Sarma B. K. Vrudhula:
An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 2057-2070 (2024)- [j32]Kyler R. Scott, Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1025-1038 (2024) - 2023
- [j31]Cheng-Yen Lee, Sunil P. Khatri:
A Digital Low Dropout (LDO) Voltage Regulator Using Pseudoflash Transistors. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 1960-1969 (2023) - [c158]Cheng-Yen Lee, Kyler R. Scott, Sunil P. Khatri, Ali Ghrayeb:
A Hardware Validation Framework for a Networked Dynamic Multi-factor Security Protocol. CommNet 2023: 1-7 - [c157]Kyler R. Scott, Sunil P. Khatri:
An Extremely Low-voltage Floating Gate Artificial Neuron. ISCAS 2023: 1-5 - [c156]Kunal Bharathi, Sunil P. Khatri, Jiang Hu:
Scaled Population Division for Approximate Computing. ISLPED 2023: 1-6 - [c155]Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator. ISQED 2023: 1-7 - 2022
- [j30]Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2968-2981 (2022) - [c154]Kyler R. Scott, Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Flash-based Current-mode IC to Realize Quantized Neural Networks. DATE 2022: 1029-1034 - [c153]Chan-Wei Hu, Jiang Hu, Sunil P. Khatri:
TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations. FPL 2022: 79-85 - [c152]Kyler R. Scott, Sunil P. Khatri:
A Flash-based Digital to Analog Converter for Low Power Applications. ICCD 2022: 1-8 - [i12]Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells. CoRR abs/2204.08070 (2022) - 2021
- [j29]Abbas A. Fairouz, Monther Abusultan, Viacheslav V. Fedorov, Sunil P. Khatri:
Hardware Acceleration of Hash Operations in Modern Microprocessors. IEEE Trans. Computers 70(9): 1412-1426 (2021) - [c151]Cheng-Yen Lee, Kunal Bharathi, Joellen Lansford, Sunil P. Khatri:
NIST-Lite: Randomness Testing of RNGs on an Energy-Constrained Platform. ICCD 2021: 41-48 - [c150]Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri:
CIDAN: Computing in DRAM with Artificial Neurons. ICCD 2021: 349-356 - [i11]Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. CoRR abs/2104.01699 (2021) - [i10]Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri:
CIDAN: Computing in DRAM with Artificial Neurons. CoRR abs/2112.00117 (2021) - 2020
- [c149]He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu:
Scaled Population Arithmetic for Efficient Stochastic Computing. ASP-DAC 2020: 611-616 - [c148]Kunal Bharathi, Jiang Hu, Sunil P. Khatri:
Scaled Population Subtraction for Approximate Computing. ICCD 2020: 348-355 - [c147]Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. ICCD 2020: 433-440 - [c146]Prasenjit Biswas, Sarit Pal, Sunil P. Khatri:
A Mathematical Framework for Exploring Protein Folding Dynamics using Probabilistic Model Checking. ICICT 2020: 114-123 - [c145]Elham Azari, Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron. ISQED 2020: 141-148
2010 – 2019
- 2019
- [j28]Andrew J. Douglass, Sunil P. Khatri:
Fast, Ring-Based Design of 3-D Stacked DRAM. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1731-1741 (2019) - [c144]He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu:
A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation. DAC 2019: 12 - [c143]Ankit Wagle, Gian Singh, Jinghua Yang, Sunil P. Khatri, Sarma B. K. Vrudhula:
Threshold Logic in a Flash. ICCD 2019: 550-558 - [i9]Ankit Wagle, Gian Singh, Jinghua Yang, Sunil P. Khatri, Sarma B. K. Vrudhula:
Threshold Logic in a Flash. CoRR abs/1910.04910 (2019) - 2018
- [j27]Ahmad Al Kawam, Sunil P. Khatri, Aniruddha Datta:
A GPU-CPU heterogeneous algorithm for NGS read alignment. Int. J. Comput. Biol. Drug Des. 11(1/2): 52-66 (2018) - [j26]Abbas A. Fairouz, Monther Abusultan, Amr Elshennawy, Sunil P. Khatri:
Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router. J. Low Power Electron. 14(3): 414-427 (2018) - [c142]Kyle Loyka, He Zhou, Sunil P. Khatri:
A Homomorphic Encryption Scheme Based on Affine Transforms. ACM Great Lakes Symposium on VLSI 2018: 51-56 - [c141]Andrew J. Douglass, Sunil P. Khatri:
Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications. ICCD 2018: 318-325 - [c140]Kunal Bharathi, Harsh Kumar, Abbas A. Fairouz, Ahmad Al Kawam, Sunil P. Khatri:
A Plain-Text Incremental Compression (PIC) Technique with Fast Lookup Ability. ICCD 2018: 389-396 - 2017
- [j25]Ahmad Al Kawam, Sunil P. Khatri, Aniruddha Datta:
A Survey of Software and Hardware Approaches to Performing Read Alignment in Next Generation Sequencing. IEEE ACM Trans. Comput. Biol. Bioinform. 14(6): 1202-1213 (2017) - [c139]He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu, Cliff C. N. Sze:
Fast and Highly Scalable Bayesian MDP on a GPU Platform. BCB 2017: 158-167 - [c138]Monther Abusultan, Sunil P. Khatri:
Design of a Flash-based Circuit for Multi-valued Logic. ACM Great Lakes Symposium on VLSI 2017: 41-46 - [c137]Kinshuk Sharma, Sunil P. Khatri:
A Robust C-element Design with Enhanced Metastability Performance. ACM Great Lakes Symposium on VLSI 2017: 95-100 - [c136]Abbas A. Fairouz, Monther Abusultan, Sunil P. Khatri:
Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors. ACM Great Lakes Symposium on VLSI 2017: 101-106 - [c135]Abbas A. Fairouz, Sunil P. Khatri:
An FPGA-Based Coprocessor for Hash Unit Acceleration. ICCD 2017: 301-304 - [c134]Andrew J. Douglass, Sunil P. Khatri:
Fast, Ring-Based Design of 3D Stacked DRAM. ICCD 2017: 665-672 - 2016
- [j24]Viacheslav V. Fedorov, Monther Abusultan, Sunil P. Khatri:
FTCAM: An Area-Efficient Flash-Based Ternary CAM Design. IEEE Trans. Computers 65(8): 2652-2658 (2016) - [c133]He Zhou, Jiang Hu, Sunil P. Khatri, Frank Liu, Cliff C. N. Sze, Mohammadmahdi R. Yousefi:
GPU acceleration for Bayesian control of Markovian genetic regulatory networks. BHI 2016: 304-307 - [c132]Venkateshwar Kottapalli, Sunil P. Khatri:
A practical methodology to validate the statistical behavior of bloom filters. CODES+ISSS 2016: 1:1-1:8 - [c131]Monther Abusultan, Suman Chakravorty, Sunil P. Khatri:
A GPU-based implementation of a sensor tasking methodology. FUSION 2016: 1398-1405 - [c130]Monther Abusultan, Sunil P. Khatri:
A flash-based digital circuit design flow. ICCAD 2016: 6 - [c129]Monther Abusultan, Sunil P. Khatri:
Implementing low power digital circuits using flash devices. ICCD 2016: 109-116 - [c128]Abbas A. Fairouz, Monther Abusultan, Sunil P. Khatri:
A novel hardware hash unit design for modern microprocessors. ICCD 2016: 412-415 - [c127]Monther Abusultan, Sunil P. Khatri:
Exploring static and dynamic flash-based FPGA design topologies. ICCD 2016: 416-419 - [c126]Monther Abusultan, Sunil P. Khatri:
A Ternary-Valued, Floating Gate Transistor-Based Circuit Design Approach. ISVLSI 2016: 719-724 - [i8]Laszlo B. Kish, Claes-Goran Granqvist, Sunil P. Khatri, Ferdinand Peper:
Response to "Comment on 'Zero and negative energy dissipation at information-theoretic erasure'". CoRR abs/1602.02638 (2016) - 2015
- [c125]Monther Abusultan, Sunil P. Khatri:
Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs. ACM Great Lakes Symposium on VLSI 2015: 111-114 - [c124]Luke Murray, Sunil P. Khatri:
An Efficient Approach to Sample On-Chip Power Supplies. ACM Great Lakes Symposium on VLSI 2015: 241-244 - [c123]Joao Marcos de Aguiar, Sunil P. Khatri:
Exploring the viability of stochastic computing. ICCD 2015: 391-394 - [i7]Laszlo B. Kish, Claes-Göran Granqvist, Sunil P. Khatri, Ferdinand Peper:
Zero and negative energy dissipation at information-theoretic erasure. CoRR abs/1507.08906 (2015) - 2014
- [c122]Monther Abusultan, Sunil P. Khatri:
Look-up Table Design for Deep Sub-threshold through Full-Supply Operation. FCCM 2014: 259-266 - [c121]Monther Abusultan, Sunil P. Khatri:
FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only). FPGA 2014: 241 - [c120]Monther Abusultan, Sunil P. Khatri:
A comparison of FinFET based FPGA LUT designs. ACM Great Lakes Symposium on VLSI 2014: 353-358 - [c119]Viacheslav V. Fedorov, Monther Abusultan, Sunil P. Khatri:
An area-efficient Ternary CAM design using floating gate transistors. ICCD 2014: 55-60 - [c118]Amr Elshennawy, Sunil P. Khatri:
An asynchronous Network-on-Chip router with low standby power. ICCD 2014: 394-399 - [c117]Kun Bian, D. M. H. Walker, Sunil P. Khatri:
Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation. VLSID 2014: 50-55 - 2013
- [j23]John F. Croix, Sunil P. Khatri, Kanupriya Gulati:
Using GPUs to Accelerate CAD Algorithms. IEEE Des. Test 30(1): 8-16 (2013) - [c116]Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra:
Exploring topologies for source-synchronous ring-based network-on-chip. DATE 2013: 1026-1031 - [c115]Rajeev Kumar, Sunil P. Khatri:
Crosstalk avoidance codes for 3D VLSI. DATE 2013: 1673-1678 - [c114]Kun Bian, D. M. H. Walker, Sunil P. Khatri, Shayak Lahiri:
Mixed structural-functional path delay test generation and compaction. DFTS 2013: 7-12 - [c113]Aditya Belsare, Steve Liu, Sunil P. Khatri:
GPU implementation of a scalable non-linear congruential generator for cryptography applications. ACM Great Lakes Symposium on VLSI 2013: 89-94 - [c112]Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra:
A source-synchronous Htree-based network-on-chip. ACM Great Lakes Symposium on VLSI 2013: 161-166 - [c111]Amr Elshennawy, Craig M. Marianno, Sunil P. Khatri:
Architecture and 3D device simulation of a PIN diode-based Gamma radiation detector. ACM Great Lakes Symposium on VLSI 2013: 329-330 - [c110]Pey-Chang Kent Lin, Sunil P. Khatri:
Noise-based algorithms for functional equivalence and tautology checking. ICCD 2013: 235-240 - [c109]Ayan Mandal, Kalyana C. Bollapalli, Nikhil Jayakumar, Sunil P. Khatri, Rabi N. Mahapatra:
A low-jitter phase-locked resonant clock generation and distribution scheme. ICCD 2013: 487-490 - 2012
- [j22]Serap A. Savari, S. M. Hossein Tabatabaei Yazdi, Navid Abedini, Sunil P. Khatri:
On Optimal and Achievable Fix-Free Codes. IEEE Trans. Inf. Theory 58(8): 5112-5129 (2012) - [c108]Pey-Chang Kent Lin, Sunil P. Khatri:
Application of logic synthesis to the understanding and cure of genetic diseases. DAC 2012: 734-740 - [c107]Pey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri:
Boolean satisfiability using noise based logic. DAC 2012: 1260-1261 - [c106]Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra:
A fast, source-synchronous ring-based network-on-chip design. DATE 2012: 1489-1494 - [c105]Pey-Chang Kent Lin, Sunil P. Khatri:
Determining gene function in boolean networks using boolean satisfiability. GENSiPS 2012: 176-179 - [c104]Bhavitavya Bhadviya, Ayan Mandal, Sunil P. Khatri:
Alleviating NBTI-induced failure in off-chip output drivers. ACM Great Lakes Symposium on VLSI 2012: 295-298 - [c103]Subramanian Poothamkurissi Swaminathan, Pey-Chang Kent Lin, Sunil P. Khatri:
Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening. ICCD 2012: 153-158 - [c102]Rajeev Kumar, Ayan Mandal, Sunil P. Khatri:
An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT. ICCD 2012: 195-200 - [c101]Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra:
Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design. ICCD 2012: 482-483 - 2011
- [j21]Laszlo B. Kish, Sunil P. Khatri, Sergey M. Bezrukov, Ferdinand Peper, Zoltan Gingl, Tamás Horváth:
Noise-based Deterministic Logic and Computing: a Brief Survey. Int. J. Unconv. Comput. 7(1-2): 101-113 (2011) - [j20]Didem Zeliha Turker, Sunil P. Khatri, Edgar Sánchez-Sinencio:
A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1225-1238 (2011) - [c100]Pey-Chang Kent Lin, Sunil P. Khatri:
Efficient cancer therapy using Boolean networks and Max-SAT-based ATPG. GENSiPS 2011: 87-90 - [c99]Pey-Chang Kent Lin, Alex Ivanov, Bradley Johnson, Sunil P. Khatri:
A novel cryptographic key exchange scheme using resistors. ICCD 2011: 451-452 - [c98]Ayan Mandal, Nikhil Jayakumar, Kalyana C. Bollapalli, Sunil P. Khatri, Rabi N. Mahapatra:
An Automated Approach for Minimum Jitter Buffered H-Tree Construction. VLSI Design 2011: 76-81 - [c97]Ayan Mandal, Vinay Karkala, Sunil P. Khatri, Rabi N. Mahapatra:
Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits. VLSI Design 2011: 82-87 - [i6]Laszlo B. Kish, Sunil P. Khatri, Sergey M. Bezrukov, Ferdinand Peper, Zoltan Gingl, Tamás Horváth:
Noise-based information processing: Noise-based logic and computing: what do we have so far? CoRR abs/1102.2256 (2011) - [i5]Pey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri:
Boolean Satisfiability using Noise Based Logic. CoRR abs/1110.0550 (2011) - 2010
- [j19]Kanupriya Gulati, Sunil P. Khatri:
Fault Table Computation on GPUs. J. Electron. Test. 26(2): 195-209 (2010) - [j18]Nikhil Jayakumar, Sunil P. Khatri:
A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty. ACM Trans. Design Autom. Electr. Syst. 16(1): 9:1-9:20 (2010) - [c96]Kalyana C. Bollapalli, Sunil P. Khatri, Laszlo B. Kish:
Implementing digital logic with sinusoidal supplies. DATE 2010: 315-318 - [c95]Navid Abedini, Sunil P. Khatri, Serap A. Savari:
A SAT-Based Scheme to Determine Optimal Fix-Free Codes. DCC 2010: 169-178 - [c94]Pey-Chang Kent Lin, Sunil P. Khatri:
Inference of gene predictor set using Boolean satisfiability. GENSiPS 2010: 1-4 - [c93]Kanupriya Gulati, Sunil P. Khatri:
Boolean satisfiability on a graphics processor. ACM Great Lakes Symposium on VLSI 2010: 123-126 - [c92]Pey-Chang Kent Lin, Sunil P. Khatri:
VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications. ACM Great Lakes Symposium on VLSI 2010: 381-384 - [c91]Vinay Karkala, Joseph Wanstrath, Travis Lacour, Sunil P. Khatri:
Efficient arithmetic sum-of-product (SOP) based Multiple Constant Multiplication (MCM) for FFT. ICCAD 2010: 735-738 - [c90]Rajesh Kumar, Sunil P. Khatri:
An efficient pulse flip-flop based launch-on-shift scan cell. ISCAS 2010: 4105-4108 - [i4]Zoltan Gingl, Sunil P. Khatri, Laszlo B. Kish:
Towards brain-inspired computing. CoRR abs/1003.3932 (2010) - [i3]Laszlo B. Kish, Sunil P. Khatri, Ferdinand Peper:
Instantaneous noise-based logic. CoRR abs/1004.2652 (2010) - [i2]Laszlo B. Kish, Sunil P. Khatri, Tamás Horváth:
Computation using Noise-based Logic: Efficient String Verification over a Slow Communication Channel. CoRR abs/1005.1560 (2010) - [i1]Laszlo B. Kish, Sunil P. Khatri, Sergey M. Bezrukov, Ferdinand Peper, Zoltan Gingl, Tamás Horváth:
Noise-based deterministic logic and computing: a brief survey. CoRR abs/1007.5282 (2010)
2000 – 2009
- 2009
- [j17]Sasidharan Ekambavanan, Rajesh Garg, Sunil P. Khatri, Krishna R. Narayanan:
Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization. J. Low Power Electron. 5(2): 157-172 (2009) - [j16]Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri:
Selective Forward Body Bias for High Speed and Low Power SRAMs. J. Low Power Electron. 5(2): 185-195 (2009) - [j15]Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas:
FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14(2): 33:1-33:11 (2009) - [j14]Suganth Paul, Nikhil Jayakumar, Sunil P. Khatri:
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 269-277 (2009) - [j13]Chunjie Duan, Victor H. Cordero Calle, Sunil P. Khatri:
Efficient On-Chip Crosstalk Avoidance CODEC Design. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 551-560 (2009) - [j12]Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi:
Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. IEEE Trans. Very Large Scale Integr. Syst. 17(6): 781-792 (2009) - [c89]Kalyana C. Bollapalli, Yiyue Wu, Kanupriya Gulati, Sunil P. Khatri, A. Robert Calderbank:
Highly parallel decoding of space-time codes on graphics processing units. Allerton 2009: 1262-1269 - [c88]Kanupriya Gulati, Sunil P. Khatri:
Accelerating statistical static timing analysis using graphics processing units. ASP-DAC 2009: 260-265 - [c87]Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry:
Fast circuit simulation on graphics processing units. ASP-DAC 2009: 403-408 - [c86]Rajesh Garg, Sunil P. Khatri:
Efficient analytical determination of the SEU-induced pulse shape. ASP-DAC 2009: 461-467 - [c85]Kanupriya Gulati, Sunil P. Khatri, Peng Li:
Closed-loop modeling of power and temperature profiles of FPGAs. FPGA 2009: 287 - [c84]Jeff L. Cobb, Kanupriya Gulati, Sunil P. Khatri:
Robust window-based multi-node technology-independent logic minimization. ACM Great Lakes Symposium on VLSI 2009: 357-362 - [c83]Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri:
Low power and high performance sram design using bank-based selective forward body bias. ACM Great Lakes Symposium on VLSI 2009: 441-444 - [c82]Kanupriya Gulati, Sunil P. Khatri:
Fault table generation using Graphics Processing Units. HLDVT 2009: 60-67 - [c81]John F. Croix, Sunil P. Khatri:
Introduction to GPU programming for EDA. ICCAD 2009: 276-280 - [c80]Rajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri:
A robust pulsed flip-flop and its use in enhanced scan design. ICCD 2009: 97-102 - [c79]Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri:
On-chip bidirectional wiring for heavily pipelined systems using network coding. ICCD 2009: 131-136 - [c78]Rajesh Garg, Sunil P. Khatri:
3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit. ICCD 2009: 498-504 - [c77]Rajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal, Sunil P. Khatri:
A radiation tolerant Phase Locked Loop design for digital electronics. ICCD 2009: 505-510 - [c76]Vinay Karkala, Kalyana C. Bollapalli, Rajesh Garg, Sunil P. Khatri:
A PLL design based on a standing wave resonant oscillator. ICCD 2009: 511-516 - [c75]Srikanth Alaparthi, Kanupriya Gulati, Sunil P. Khatri:
Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation. ISCAS 2009: 2225-2228 - [c74]Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya:
Design and implementation of a sub-threshold BFSK transmitter. ISQED 2009: 664-672 - [c73]Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi:
SEU hardened clock regeneration circuits. ISQED 2009: 806-813 - [c72]Laszlo B. Kish, Sergey M. Bezrukov, Sunil P. Khatri, Zoltan Gingl, S. Sethuraman:
Noise-Based Logic and Computing: From Boolean Logic Gates to Brain Circuitry and Its Possible Hardware Realization. IWNC 2009: 13-22 - 2008
- [j11]Kanupriya Gulati, Mandar Waghmode, Sunil P. Khatri, Weiping Shi:
Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. IET Comput. Digit. Tech. 2(3): 214-229 (2008) - [j10]Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker:
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integr. 41(3): 399-412 (2008) - [j9]Sabyasachi Das, Sunil P. Khatri:
A Timing-Driven Approach to Synthesize Fast Barrel Shifters. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 31-35 (2008) - [j8]Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri:
SAT-based ATPG using multilevel compatible don't-cares. ACM Trans. Design Autom. Electr. Syst. 13(2): 24:1-24:18 (2008) - [j7]Sabyasachi Das, Sunil P. Khatri:
Resource sharing among mutually exclusive sum-of-product blocks for area reduction. ACM Trans. Design Autom. Electr. Syst. 13(3): 51:1-51:7 (2008) - [j6]Sabyasachi Das, Sunil P. Khatri:
A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 326-331 (2008) - [j5]Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri:
Dynamically De-Skewable Clock Distribution Methodology. IEEE Trans. Very Large Scale Integr. Syst. 16(9): 1220-1229 (2008) - [c71]Kanupriya Gulati, Sunil P. Khatri:
Towards acceleration of fault simulation using graphics processing units. DAC 2008: 822-827 - [c70]Rajesh Garg, Charu Nagpal, Sunil P. Khatri:
A fast, analytical estimator for the SEU-induced pulse width in combinational designs. DAC 2008: 918-923 - [c69]Chunjie Duan, Chengyu Zhu, Sunil P. Khatri:
Forbidden transition free crosstalk avoidance CODEC design. DAC 2008: 986-991 - [c68]Charu Nagpal, Rajesh Garg, Sunil P. Khatri:
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. DATE 2008: 354-359 - [c67]Chunjie Duan, Sunil P. Khatri:
Energy Efficient and High Speed On-Chip Ternary Bus. DATE 2008: 515-518 - [c66]Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri:
A Single-supply True Voltage Level Shifter. DATE 2008: 979-984 - [c65]Victor H. Cordero Calle, Sunil P. Khatri:
Clock Distribution Scheme using Coplanar Transmission Lines. DATE 2008: 985-990 - [c64]Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri:
A robust, fast pulsed flip-flop design. ACM Great Lakes Symposium on VLSI 2008: 119-122 - [c63]Kanupriya Gulati, Sunil P. Khatri:
Improving FPGA routability using network coding. ACM Great Lakes Symposium on VLSI 2008: 147-150 - [c62]Suganth Paul, Rajesh Garg, Sunil P. Khatri:
Pipelined network of PLA based circuit design. ACM Great Lakes Symposium on VLSI 2008: 213-218 - [c61]Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng:
A lithography-friendly structured ASIC design approach. ACM Great Lakes Symposium on VLSI 2008: 315-320 - [c60]Rajesh Garg, Sunil P. Khatri:
A novel, highly SEU tolerant digital circuit design approach. ICCD 2008: 14-20 - [c59]Rajesh Garg, Peng Li, Sunil P. Khatri:
Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). ISCAS 2008: 1788-1791 - [c58]Sabyasachi Das, Sunil P. Khatri:
A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. VLSI Design 2008: 572-579 - [c57]Sabyasachi Das, Sunil P. Khatri:
A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions. VLSI Design 2008: 635-640 - [c56]Sabyasachi Das, Sunil P. Khatri:
An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products. VLSI Design 2008: 653-659 - 2007
- [j4]Nikhil Jayakumar, Sunil P. Khatri:
A Predictably Low-Leakage ASIC Design Style. IEEE Trans. Very Large Scale Integr. Syst. 15(3): 276-285 (2007) - [j3]Vijay Nagarajan, Stefan Laendner, Nikhil Jayakumar, Olgica Milenkovic, Sunil P. Khatri:
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems. J. VLSI Signal Process. 49(1): 185-206 (2007) - [c55]Nikhil Jayakumar, Sunil P. Khatri:
An algorithm to minimize leakage through simultaneous input vector control and circuit modification. DATE 2007: 618-623 - [c54]Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri:
Toggle Equivalence Preserving (TEP) Logic Optimization. DSD 2007: 271-279 - [c53]Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri:
A Structured ASIC Design Approach Using Pass Transistor Logic. ISCAS 2007: 1787-1790 - [c52]Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri:
A methodology for interconnect dimension determination. ISPD 2007: 189-195 - 2006
- [c51]Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri:
Controlling inductive cross-talk and power in off-chip buses using CODECs. ASP-DAC 2006: 850-855 - [c50]Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri:
A PLA based asynchronous micropipelining approach for subthreshold circuit design. DAC 2006: 419-424 - [c49]Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi:
A design approach for radiation-hard digital electronics. DAC 2006: 773-778 - [c48]Brock J. LaMeres, Sunil P. Khatri:
Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. DATE 2006: 522-527 - [c47]Bo Shen, Sunil P. Khatri, Takis Zourntos:
Implementation of MOSFET based capacitors for digital applications. ACM Great Lakes Symposium on VLSI 2006: 180-186 - [c46]Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri:
A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI 2006: 217-222 - [c45]Scott J. Campbell, Sunil P. Khatri:
Resource and delay efficient matrix multiplication using newer FPGA devices. ACM Great Lakes Symposium on VLSI 2006: 308-311 - [c44]Euncheol Kim, Nikhil Jayakumar, Pankaj Bhagawat, Anand Selvarathinam, Gwan Choi, Sunil P. Khatri:
A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes. ICASSP (3) 2006: 972-975 - [c43]Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson:
Network coding for routability improvement in VLSI. ICCAD 2006: 820-823 - [c42]Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri:
On the Improvement of Statistical Static Timing Analysis. ICCD 2006: 37-42 - [c41]Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri:
CMOS Comparators for High-Speed and Low-Power Applications. ICCD 2006: 76-81 - [c40]Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi:
An Efficient, Scalable Hardware Engine for Boolean SATisfiability. ICCD 2006: 326-331 - [c39]Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri:
Memory-based crosstalk canceling CODECs for on-chip buses. ISCAS 2006 - [c38]Chunjie Duan, Sunil P. Khatri:
Computing during supply voltage switching in DVS enabled real-time processors. ISCAS 2006 - [c37]Rajesh Garg, Sunil P. Khatri:
Generalized buffering of PTL logic stages using Boolean division. ISCAS 2006 - [c36]Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri:
A probabilistic method to determine the minimum leakage vector for combinational designs. ISCAS 2006 - [c35]Kanupriya Gulati, M. Lovell, Sunil P. Khatri:
Efficient don't care computation for hierarchical designs. ISCAS 2006 - 2005
- [c34]Van R. Culver, Sunil P. Khatri:
A dynamic voltage scaling algorithm for energy reduction in hard real-time systems. ASP-DAC 2005: 842-845 - [c33]Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri:
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. DAC 2005: 43-46 - [c32]Nikhil Jayakumar, Sunil P. Khatri:
A variation tolerant subthreshold design approach. DAC 2005: 716-719 - [c31]Brock J. LaMeres, Sunil P. Khatri:
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission. DATE 2005: 1318-1323 - [c30]John Valavi, Nikhil Saluja, Sunil P. Khatri:
A Boolean satisfiability based solution to the routing and wavelength assignment problem in optical telecommunication networks. ICC 2005: 1802-1806 - [c29]Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert:
Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD 2005: 592-596 - [c28]Seraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra:
X-Routing using Two Manhattan Route Instances. ICCD 2005: 45-52 - [c27]Nikhil Jayakumar, Sunil P. Khatri:
Minimum Energy Near-threshold Network of PLA based Design. ICCD 2005: 399-404 - [c26]Brock J. LaMeres, Sunil P. Khatri:
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. ICCD 2005: 683-688 - [c25]Brock J. LaMeres, Sunil P. Khatri:
Performance model for inter-chip communication considering inductive cross-talk and cost. ISCAS (4) 2005: 4130-4133 - [c24]Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri:
An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. ISLPED 2005: 111-114 - [c23]Nikhil Saluja, Sunil P. Khatri:
Efficient SAT-based combinational ATPG using multi-level don't-cares. ITC 2005: 10 - [c22]Edward Hursey, Nikhil Jayakumar, Sunil P. Khatri:
Non-Manhattan Routing Using a Manhattan Router. VLSI Design 2005: 445-450 - 2004
- [j2]Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
SPFD-based wire removal in standard-cell and network-of-PLA circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1020-1030 (2004) - [c21]Nikhil Saluja, Sunil P. Khatri:
A robust algorithm for approximate compatible observability don't care (CODC) computation. DAC 2004: 422-427 - [c20]Chunjie Duan, Sunil P. Khatri:
Exploiting Crosstalk to Speed up On-Chip Buse. DATE 2004: 778-783 - [c19]Vijay Nagarajan, Nikhil Jayakumar, Sunil P. Khatri, Olgica Milenkovic:
High-throughput VLSI implementations of iterative decoders and related code construction problems. GLOBECOM 2004: 361-365 - [c18]Nikhil Jayakumar, Sunil P. Khatri:
A metal and via maskset programmable VLSI design methodology using PLAs. ICCAD 2004: 590-594 - [c17]Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri:
A novel clock distribution and dynamic de-skewing methodology. ICCAD 2004: 626-631 - 2003
- [c16]Bruce Gamache, Zachary Pfeffer, Sunil P. Khatri:
A fast ternary CAM design for IP networking applications. ICCCN 2003: 434-439 - [c15]Jianjian Bian, Sunil P. Khatri:
IP routing table compression using ESPRESSO-MV. ICON 2003: 167-172 - [c14]Nikhil Jayakumar, Sunil P. Khatri:
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. ISLPED 2003: 128-133 - 2002
- [j1]Sabyasachi Das, Sunil P. Khatri:
An efficient and regular routing methodology for datapath designsusing net regularity extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 93-101 (2002) - 2001
- [c13]Chunjie Duan, Anup Tirumala, Sunil P. Khatri:
Analysis and avoidance of cross-talk in on-chip buses. Hot Interconnects 2001: 133-138 - [c12]Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli:
Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement. ICCAD 2001: 224-231 - [c11]Sabyasachi Das, Sunil P. Khatri:
A regularity-driven fast gridless detailed router for high frequency datapath designs. ISPD 2001: 130-135 - 2000
- [c10]Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. ICCAD 2000: 412-418 - [c9]Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. ICCD 2000: 494-503
1990 – 1999
- 1999
- [c8]Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli:
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. DAC 1999: 491-496 - [c7]Robert K. Brayton, Sunil P. Khatri:
Multi-Valued Logic Synthesis. VLSI Design 1999: 196-105 - [c6]Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential Multi-Valued Network Simplification using Redundancy Removal. VLSI Design 1999: 206-211 - 1996
- [c5]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS: A System for Verification and Synthesis. CAV 1996: 428-432 - [c4]Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Engineering Change in a Non-Deterministic FSM Setting. DAC 1996: 451-456 - [c3]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS. FMCAD 1996: 248-256 - [c2]Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita:
Decomposition Techniques for Efficient ROBDD Construction. FMCAD 1996: 419-434 - [c1]Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design 1996: 249-253
Coauthor Index
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