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ORCIDIshwar Parulkar
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2010 – 2019
- 2010
[c15]Mehdi Baradaran Tahoori, Ishwar Parulkar, Dan Alexandrescu, Kevin Granlund, Allan Silburt, Bapi Vinnakota:
Panel: Reliability of data centers: Hardware vs. software. DATE 2010: 1620
2000 – 2009
- 2009
- [j5]Ishwar Parulkar, Babu Turumella:
Comprehensive Approach to High-Performance Server Chipset Debug. IEEE Des. Test Comput. 26(3): 70-77 (2009) - [j4]Georgios K. Konstadinidis, Marc Tremblay, Shailender Chaudhry, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar:
Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor. IEEE J. Solid State Circuits 44(1): 7-17 (2009) - [c14]Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
, Ishwar Parulkar:
Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors. ETS 2009: 33-38 - 2008
- [c13]Cristian Constantinescu, Ishwar Parulkar, R. Harper, Sarah Michalak:
Silent Data Corruption - Myth or reality? DSN 2008: 108-109 - [c12]Georgios K. Konstadinidis, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar:
Implementation of a Third-Generation 16-Core 32-Thread Chip-Multithreading SPARCs® Processor. ISSCC 2008: 84-85 - [c11]Ishwar Parulkar, Sriram Anandakumar, Gaurav Agarwal, Gordon Liu, Krishna Rajan, Frank Chiu, Rajesh Pendurkar:
DFX of a 3rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor. ITC 2008: 1-10 - 2005
- [c10]Ishwar Parulkar, Robert Cypher:
Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems. IOLTS 2005: 74-77 - [c9]Iain Robertson, Graham Hetherington, Tom Leslie, Ishwar Parulkar, Ronald Lesnikoski:
Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems. ITC 2005: 8 - [c8]Ishwar Parulkar, Dawei Huang, Leandro Chua Jr., Drew Doblar:
Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in field. ITC 2005: 9 - 2003
- [c7]Peter Dahlgren, Paul Dickinson, Ishwar Parulkar:
Latch Divergency In Microprocessor Failure Analysis. ITC 2003: 755-763 - 2002
- [c6]Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar:
A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors. ITC 2002: 726-735 - 2001
- [j3]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Introducing redundant computations in RTL data paths for reducing BIST resources. ACM Trans. Design Autom. Electr. Syst. 6(3): 423-445 (2001)
1990 – 1999
- 1998
- [j2]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Allocation Techniques for Reducing BIST Area Overhead of Data Paths. J. Electron. Test. 13(2): 149-166 (1998) - [j1]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Estimation of BIST Resources During High-Level Synthesis. J. Electron. Test. 13(3): 221-237 (1998) - [c5]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Introducing Redundant Computations in a Behavior for Reducing BIST Resources. DAC 1998: 548-553 - [c4]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Scheduling and Module Assignment for Reducing Bist Resources. DATE 1998: 66-73 - 1996
- [c3]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Lower Bounds on Test Resources for Scheduled Data Flow Graphs. DAC 1996: 143-148 - 1995
- [c2]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. DAC 1995: 395-401 - 1994
- [c1]Ishwar Parulkar, Melvin A. Breuer, Charles Njinda:
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. DAC 1994: 345-356
Coauthor Index
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