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2020 – today
- 2020
[c8]Jian-Wei Su
, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang:
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. ISSCC 2020: 240-242
2010 – 2019
- 2019
- [c7]Xin Si, He Qian, Meng-Fan Chang, Cheng-Xin Xue, Jian-Wei Su, Zhixiao Zhang, Sih-Han Li, Shyh-Shyuan Sheu, Heng-Yuan Lee, Ping-Cheng Chen, Huaqiang Wu:
Circuit Design Challenges in Computing-in-Memory for AI Edge Devices. ASICON 2019: 1-4 - [c6]Chih-Cheng Chang, Ming-Hung Wu, Jia-Wei Lin, Chun-Hsien Li, Vivek Parmar, Heng-Yuan Lee, Jeng-Hua Wei, Shyh-Shyuan Sheu, Manan Suri, Tian-Sheuan Chang, Tuo-Hung Hou:
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge. DAC 2019: 30 - 2018
- [j5]Tsai-Kan Chien, Lih-Yih Chiou, Chi-Shian Chang, Jing-Yu Huang, Chung-Han Wu, Heng-Yuan Lee, Shyh-Shyuan Sheu:
Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F2/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM. IEEE Trans. Circuits Syst. II Express Briefs 65-II(9): 1234-1238 (2018) - 2017
- [c5]Rui Liu, Heng-Yuan Lee, Shimeng Yu:
Analyzing inference robustness of RRAM synaptic array in low-precision neural network. ESSDERC 2017: 18-21 - 2015
- [c4]Stefano Ambrogio, Simone Balatti, Zhongqiang Wang, Yu-Sheng Chen, Heng-Yuan Lee, Frederick T. Chen, Daniele Ielmini:
Data retention statistics and modelling in HfO2 resistive switching memories. IRPS 2015: 7 - [c3]Meng-Fan Chang, Chien-Chen Lin, Albert Lee, Chia-Chen Kuo, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu, Pei-Ling Tseng, Heng-Yuan Lee, Tzu-Kun Ku:
17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time. ISSCC 2015: 1-3 - 2014
- [c2]Wen-Pin Lin, Shyh-Shyuan Sheu, Chia-Chen Kuo, Pei-Ling Tseng, Meng-Fan Chang, Keng-Li Su, Chih-Sheng Lin, Kan-Hsueh Tsai, Sih-Han Lee, Szu-Chieh Liu, Yu-Sheng Chen, Heng-Yuan Lee, Ching-Chih Hsu, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao:
A nonvolatile look-up table using ReRAM for reconfigurable logic. A-SSCC 2014: 133-136 - 2013
- [j4]Meng-Fan Chang, Shyh-Shyuan Sheu, Ku-Feng Lin, Che-Wei Wu, Chia-Chen Kuo, Pi-Feng Chiu, Yih-Shan Yang, Yu-Sheng Chen, Heng-Yuan Lee, Chen-Hsin Lien, Frederick T. Chen, Keng-Li Su, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai:
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes. IEEE J. Solid State Circuits 48(3): 878-891 (2013) - 2012
- [j3]H.-S. Philip Wong, Heng-Yuan Lee, Shimeng Yu, Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T. Chen, Ming-Jinn Tsai:
Metal-Oxide RRAM. Proc. IEEE 100(6): 1951-1970 (2012) - 2011
- [j2]Frederick T. Chen, Heng-Yuan Lee, Yu-Sheng Chen, Yenya Hsu, Lijie Zhang, Pang-Shiu Chen, Weisu Chen, Peiyi Gu, Wenhsing Liu, Sumin Wang, Chen-Han Tsai, Shyh-Shyuan Sheu, Ming-Jinn Tsai, Ru Huang:
Resistance switching for RRAM applications. Sci. China Inf. Sci. 54(5): 1073-1086 (2011) - [j1]Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Meng-Fan Chang, Pei-Chia Chiang, Wen-Pin Lin, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Frederick T. Chen, Ming-Jinn Tsai:
Fast-Write Resistive RAM (RRAM) for Embedded Applications. IEEE Des. Test Comput. 28(1): 64-71 (2011) - [c1]Shyh-Shyuan Sheu, Meng-Fan Chang, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Peiyi Gu, Sumin Wang, Frederick T. Chen, Keng-Li Su, Chen-Hsin Lien, Kuo-Hsing Cheng, Hsin-Tun Wu, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai:
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. ISSCC 2011: 200-202
Coauthor Index
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