default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDJournal of Electronic Testing, Volume 6
Volume 6, Number 1, February 1995
- Vishwani D. Agrawal:
Editorial. 5-6 - Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults. 7-22 - Shyang-Tai Su, Rafic Z. Makki, H. Troy Nagle
:
Transient power supply current monitoring - A new test method for CMOS VLSI circuits. 23-43 - Konstantin Keutner, Erwin Trischler:
Efficient sensitization of multi-bit-paths for testing embedded modules in synchronous sequential circuits. 45-58 - Kent L. Einspahr, Sharad C. Seth:
A switch-level test generation system for synchronous and asynchronous circuits. 59-73 - D. Lambidonis, Vinod K. Agarwal, André Ivanov, Dhiren Xavier:
A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes. 75-84 - Oliver F. Haberl, Thomas Kropf:
HIST: A hierarchical self test methodology for chips, boards, and systems. 85-106 - Fidel Muradali, Takao Nishida, Tsuguo Shimizu:
A structure and technique for pseudorandom-based testing of sequential circuits. 107-115 - Soon Fatt Yoon:
Some observations from interrupted lifetest of GaInAsP/InP inverted-rib laser diodes. 117-125 - Joan Figueras, Michel Renovell:
Current testing in dynamic CMOS circuits. 127-131 - Maria J. Avedillo, José M. Quintana, José Luis Huertas:
Constrained state assignment of easily testable FSMs. 133-138 - Slawomir Pilarski:
Comments on "Aliasing Properties of Circular MISRs". 139-140 - Geetani Edirisooriya, John P. Robinson:
Authors' reply to comments on "Aliasing Properties of Circular MISRs". 141-142
Volume 6, Number 2, April 1995
- Vishwani D. Agrawal:
Editorial. 147 - William P. Marnane, Will R. Moore:
Testing VLSI regular arrays. 153-177 - Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto:
Testability of artificial neural networks: A behavioral approach. 179-190 - Manoj Sachdev:
Reducing the CMOS RAM test complexity withIDDQ and voltage testing. 191-202 - Giacomo Buonanno, Franco Fummi, Donatella Sciuto:
TIES: A testability increase expert system for VLSI design. 203-217 - Ilana David, Ran Ginosar, Michael Yoeli:
Self-timed is self-checking. 219-228 - Dimitrios Kagaris, Spyros Tragoudas:
Avoiding linear dependencies in LFSR test pattern generators. 229-241 - Shujian Zhang, Jon C. Muzio:
Evaluating the safety of self-checking circuits. 243-253 - Kevin Cattell, Shujian Zhang:
Minimal cost one-dimensional linear hybrid cellular automata of degree through 500. 255-258
Volume 6, Number 3, June 1995
- Vishwani D. Agrawal:
Editorial. 263 - Manoj Sachdev:
A realistic defect oriented testability methodology for analog circuits. 265-276 - Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
An advanced diagnostic method for delay faults in combinational faulty circuits. 277-294 - Michael Nicolaidis:
Efficient UBIST implementation for microprocessor sequencing parts. 295-312 - Beyin Chen, Chung-Len Lee:
Universal test set generation for CMOS circuits. 313-323 - H. Zhou, Howard C. Card, Gregory E. Bridges:
Parallel pseudorandom number generation in GaAs cellular automata for high speed circuit testing. 325-330 - Kanji Hirabayashi:
A parametric yield model. 331-332 - Wuudiann Ke, Premachandran R. Menon:
Multifault and delay-fault testability of multilevel circuits. 333-336
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-11 20:46 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
