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ORCIDVTS 1993: Atlantic City, NJ, USA
- 11th IEEE VLSI Test Symposium (VTS'93), 6 Apr 1993-8 Apr 1993, Atlantic City, NJ, USA. IEEE Computer Society 1993, ISBN 0-8186-3830-3
- Yervant Zorian:
A distributed BIST control scheme for complex VLSI devices. 4-9 - Geetani Edirisooriya, Samantha Edirisooriya, John P. Robinson:
A new built-in self-test method based on prestored testing. 10-16 - Yuejian Wu, André Ivanov:
Minimal hardware multiple signature analysis for BIST. 17-20 - Eugeni Isern, Joan Figueras:
Analysis of redundant structures in combinational circuits. 21-23 - Sreejit Chakravarty, Paul J. Thadikaran:
Simulation and generation of IDDQ tests for bridging faults in combinational circuits. 25-32 - Fabian Luis Vargas, Michael Nicolaidis, B. Hamdi:
Quiescent current estimation based on quality requirements. 33-39 - Lee Whetsel:
An IEEE 1149.1 based voltmeter/oscilloscope in a chip. 40-46 - Fadi Y. Busaba, Parag K. Lala:
Input and output encoding techniques for on-line error detection in combinational logic circuits. 48-54 - Guoning Liao:
Error detection, fault location and reconfiguration for 2D mesh processing element arrays for digital signal processing. 55-61 - Uwe Sparmann:
On the check base selection problem for fast adders. 62-65 - Michael Nicolaidis:
Finitely self-checking circuits and their application on current sensors. 66-69 - Robert H. Klenke, Ronald D. Williams, James H. Aylor:
Parallelization methods for circuit partitioning based parallel automatic test pattern generation. 71-78 - Kyuchull Kim, Kewal K. Saluja:
CCSTG: an efficient test pattern generator for sequential circuits. 79-84 - Haluk Konuk, Tracy Larrabee:
Explorations of sequential ATPG using Boolean satisfiability. 85-90 - Alvin Jee, F. Joel Ferguson:
Carafe: an inductive fault analysis tool for CMOS VLSI circuits. 92-98 - Adit D. Singh, C. Mani Krishna:
The effect of defect clustering on test transparency and defect levels. 99-105 - Samir B. Naik, Wojciech P. Maly:
Computer-aided failure analysis of VLSI circuits using IDDQ testing. 106-108 - Savio N. Chau:
Fault injection scan design for enhanced VLSI design verification. 109-111 - Scott F. Midkiff, S. Wayne Bollinger:
Classification of bridging faults in CMOS circuits: experimental results and implications for test. 112-115 - Chennian Di, Jochen A. G. Jess:
On CMOS bridge fault modeling and test pattern evaluation. 116-119 - Friedrich Taenzler, Thomas Novak, Erich Kubalek:
Contactless characterization of microwave integrated circuits by device internal indirect electro-optic probing. 120-122 - Kamal K. Varma, Praveen Vishakantaiah, Jacob A. Abraham:
Generation of testable designs from behavioral descriptions using high level synthesis tools. 124-130 - Sandip Kundu, Ankan K. Pramanick:
Testability preserving Boolean transforms for logic synthesis. 131-138 - Jaushin Lee, Janak H. Patel:
Testability analysis based on structural and behavioral information. 139-146 - Xiao Sun, Fabrizio Lombardi:
On the design for testability of sequential circuits. 147-150 - Shunichi Toida:
Revisiting shift register realization for ease of test generation and testing. 151-153 - Mohamed Jamoussi, Bozena Kaminska:
Controllability and observability measures for functional-level testability evaluation. 154-157 - Dan Lamet, James F. Frenzel:
Defect-tolerant cache memory design. 159-163 - William R. Reohr, Yuen H. Chan, Donald W. Plass, Antonio Pelella, Philip T. Wu:
Design SRAMs for burn-in. 164-170 - Jean-Luc Peter:
ECC design of a custom DRAM storage unit. 171-173 - Hussain Al-Asaad, Edward C. Czeck:
Concurrent error correction in iterative circuits by recomputing with partitioning and voting. 174-177 - Murali M. R. Gala, Karan L. Watson, Don E. Ross:
Testability of one dimensional ILAs under multiple faults. 178-181 - Hussam Y. Abujbara, Sami A. Al-Arian:
Degrading fault model for WSI interconnection lines. 182-185 - Radu Marculescu:
Worst-case analysis for pseudorandom testing. 187-193 - Ravishankar Kodavarti, Don E. Ross:
Signal probability calculations using partial functional manipulation. 194-200 - Beena Vasudevan, Don E. Ross, Murali M. R. Gala, Karan L. Watson:
LFSR based deterministic hardware for at-speed BIST. 201-207 - Christian Dufaza, Cyril Chevalier, Lew Fock Chong Lew Yan Voon:
LFSROM an algorithm for automatic design synthesis of hardware test pattern generator. 208-214 - Wolfgang Vermeiren, Wolfgang Straube, Günter Elst:
Improvement of analog circuit fault detectability using fault detection observers. 218-224 - Yunsheng Lu, Ramaswami Dandapani:
Hard faults diagnosis in analog circuits using sensitivity analysis. 225-229 - William H. Kao, Jean Qincui Xia:
Automatic synthesis of DUT board circuits for testing of mixed signal ICs. 230-236 - Masatoshi Arai, Tohru Nakagawa, Hajime Kitagawa:
A neural inverse function for automatic test pattern generation using strictly digital neural networks. 238-243 - Sang-Hoon Song, Larry L. Kinney:
Incremental test pattern generation. 244-250 - Sanjay Srinivasan, Gnanasekaran Swaminathan, James H. Aylor, M. Ray Mercer:
Combinational circuit ATPG using binary decision diagrams. 251-258 - Krishnendu Chakrabarty, John P. Hayes:
Aliasing-free error detection (ALFRED). 260-266 - Shou-ping Feng, Toru Fujiwara, Tadao Kasami, Kazuhiko Iwasaki:
On the maximum value of aliasing probabilities for single input signature registers. 267-274 - Geetani Edirisooriya, Samantha Edirisooriya, John P. Robinson:
Time and space correlated errors in signature analysis. 275-281 - Irith Pomeranz, Sudhakar M. Reddy:
Aliasing computation using fault simulation with fault dropping. 282-288 - F. Joel Ferguson:
Physical design for testability for bridges in CMOS circuits. 290-295 - Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya:
Testable design for BiCMOS stuck-open fault detection. 296-302 - Sandip Kundu:
On diagnosis of faults in a scan-chain. 303-308 - Jaushin Lee, Vivek Chickermane, Janak H. Patel:
Impact of high level functional constraints on testability. 309-312 - Vishwani D. Agrawal, Tapan J. Chakraborty:
Partial scan testing with single clock control. 313-315 - Dinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly:
Estimation of reject ratio in testing of combinatorial circuits. 319-325 - Zafar Hasan, Maciej J. Ciesielski:
Functional verification and simulation of FSM networks. 326-332 - Kumar Venkat:
A structured design for test methodology. 333-336 - Constantine Stivaros:
A model for testing reliable VLSI routing architectures. 337-339 - Christopher A. Ryan, Joseph G. Tront:
On parallel switch level fault simulation. 341-347 - Yinghua Min, Zhongcheng Li:
Evaluation of test generation algorithms. 348-350 - Jürgen Alt, Udo Mahlstedt:
Simulation of non-classical faults on the gate level-fault modeling. 351-354 - Erik H. Ingermann, James F. Frenzel:
Sensitivity analysis of a radiation immune CMOS logic family under defect conditions. 355-357 - Stephen M. Dunn, D. G. Balazich, Lawrence K. Lange, Charlotte C. Montillo:
Pattern generator card, emulation, and debug. 358-360
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