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ORCIDSoC 2005, Tampere, Finland
- Proceedings of the 2005 International Symposium on System-on-Chip, Tampere, Finland, November 15-17, 2005. IEEE 2005, ISBN 0-7803-9294-9
- Srinivasan Murali:
Design Methodologies and CAD Tool Flows for Networks on Chips. 1 - Jari Nurmi
:
Network-on-Chip: A New Paradigm for System-on-Chip Design. 2-6 - Bill Chown:
System-level modeling and validation increase design productivity and save errors. 7 - Chris Rowen, Ashish Dixit, Steve Leibson:
Low-Power SOC Design Using Configurable Processors-The Non-Nuclear Option. 8-13 - Panu Hämäläinen, Ning Liu, Marko Hännikäinen, Timo D. Hämäläinen:
Acceleration of Modular Exponentiation on System-on-a-Programmable-Chip. 14-17 - Tero Säntti, Juha Plosila:
Instruction Folding for an Asynchronous Java Co-Processor. 18-21 - Natale Barsotti, Riccardo Mariani, Matteo Martinelli, Mario Pasquariello:
Dynamic Verification of OCP-based SoC. 22 - Guy Gogniat, Tilman Wolf, Wayne P. Burleson:
Reconfigurable Security Primitive for Embedded Systems. 23-28 - Claudio Brunelli, Fabio Garzia, Jari Nurmi, Claudio Mucci, Fabio Campi, Davide Rossi:
A FPGA Implementation of An Open-Source Floating-Point Computation System. 29-32 - SangKyu Lee, JeongEun Kim, Namsub Kim, Jinsang Kim, Won-Kyung Cho:
Multiplierless Reconfigurable Processing Element And Its Applications to DSP Kernels. 33-36 - Stefano Zammattio:
SOPC Builder, a Novel Design Methodology for IP Integration. 37 - Tommi J. Zetterman, Jukka T. Liimatainen, Jyrki T. Alamaunu:
Proof of Concept for Low-power Digital Asynchronous IC Design. 38-41 - Eduardo Braulio Wanderley Netto, Eduardo Afonso Billo, Rodolfo Azevedo:
Exploiting the Area X Performance Trade-off with Code Compression. 42-45 - Kimmo Puusaari:
Application Specific Instruction Set Processor Microarchitecture for UTMS-FDD Cell Search. 46-49 - Petri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen:
Performance Modeling and Reporting for the UML 2.0 Design of Embedded Systems. 50-53 - Adeoye Olugbon, Tughrul Arslan, Iain Lindsay, Scott MacDougall:
Providing Compilers and Application Program Support for Reconfigurable SoCs: Radical but Overdue. 54-57 - Ping Yeung, Kenneth Larsen:
Practical Assertion-based Formal Verification for SoC Designs. 58-61 - Martin Holzer, Markus Rupp:
Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips. 62-65 - Chantal Ykman-Couvreur, Erik Brockmeyer, Vincent Nollet, Théodore Marescaux, Francky Catthoor, Henk Corporaal:
Design-Time Application Exploration for MP-SoC Customized Run-Time Management. 66-69 - Gerard J. M. Smit, Eberhard Schüler, Jürgen Becker, Jérôme Quévremont, Werner Brugger:
Overview of the 4S Project. 70-73 - Arnaud Rivaton, Jérôme Quévremont, Qiwei Zhang, Pascal T. Wolkotte, Gerard J. M. Smit:
Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures. 74-77 - Lodewijk T. Smit, Johann L. Hurink, Gerard J. M. Smit:
Run-time Mapping of Applications to a Heterogeneous SoC. 78-81 - Pascal T. Wolkotte, Gerard J. M. Smit, Nikolay Kavaldjiev, Jens E. Becker, Jürgen Becker:
Energy Model of Networks-on-Chip and a Bus. 82-85 - Xiaotao Chang, Dongrui Fan, Yinhe Han, Zhimin Zhang:
SoC Leakage Power Reduction Algorithm by Input Vector Control. 86-89 - Martti Forsell:
ParLe - A Parallel Computing Learning Set for MPSOCs/NOCs. 90-95 - Johanna Tuominen, Tero Säntti, Juha Plosila:
Towards a Formal Power Estimation Framework for Hardware Systems. 96-99 - Jae-Gon Lee, Ki-Yong Ahn, Chong-Min Kyung:
Predictive Synchronization Scheme between Simulator And Accelerator Free from Performance Deterioration. 100-103 - Soujanna Sarkar, Sanjay Shinde, Subash Chandar G.:
An Effective IP Reuse Methodology for Quality System-on-Chip Design. 104-107 - Jouni Riihimäki, Petri Kukkala, Tero Kangas, Marko Hännikäinen, Timo D. Hämäläinen:
Interfacing UML 2.0 for Multiprocessor System-on-Chip Design Flow. 108-111 - Antonis Papanikolaou, F. Starzer, Miguel Miranda, Koenraad De Bosschere, Francky Catthoor:
Architectural and Physical Design Optimizations for Efficient Intra-tile Communication. 112-115 - Tomi Westerlund, Juha Plosila:
Formal Modelling of Synchronous Hardware Components for System-on-Chip. 116-119 - Petri Isomäki, Nastooh Avessta:
Rapid Refinable SoC SDR Design. 120-123 - Ethiopia Nigussie, Juha Plosila, Jouni Isoaho:
Reliable Asynchronous Links for SoC. 124-127 - Rafal P. Jastrzebski, Riku Pöllänen, Olli Pyrhönen:
Analysis of System Architecture of FPGA-based Embedded Controller for Magnetically Suspended Rotor. 128-132 - Antti Innamaa:
FPGA Prototyping: Untapping Potential within the Multimillion-Gate System-on-Chip Design Space. 133-136 - Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. 137-140 - Lasse Harju, Jari Nurmi:
A Synchronization Coprocessor Architecture for WCDMA/OFDM Mobile Terminal Implementations. 141-145 - Heikki Orsila, Tero Kangas, Timo D. Hämäläinen:
Hybrid Algorithm for Mapping Static Task Graphs on Multiprocessor SoCs. 146-150 - Senthilkumar Jayapal, Shanthi Sudalaiyandi, Yiannos Manoli:
Efficiency of Leakage Reduction Techniques on Different Static Logic Styles for Embedded Portable Applications with High Standby to Active Time Ratio. 151-154 - Xin Wang, Jari Nurmi:
An On-Chip CDMA Communication Network. 155-160 - Felipe Klein, Rodolfo Azevedo, Guido Araujo:
High-Level Switching Activity Prediction Through Sampled Monitored Simulation. 161-166 - Jari Kreku, Matti Eteläperä, Juha-Pekka Soininen:
Exploitation of UML 2.0 - Based Platform Service Model and SystemC Workload Simulation in MPEG-4 Partitioning. 167-170 - Tobias Bjerregaard, Shankar Mahadevan, Rasmus Grøndahl Olsen, Jens Sparsø:
An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip. 171-174 - Adeoye Olugbon, Tughrul Arslan, Iain Lindsay:
A Formal Approach to Virtualisation and Provisioning in AMBA AHB-based Reconfigurable Systems-on-Chip. 175-178 - Kashif Virk, Knud Hansen, Jan Madsen:
System-level Modeling of Wireless Integrated Sensor Networks. 179-182 - Steve B. Furber, John Bainbridge:
Future Trends in SoC Interconnect.
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