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ORCIDICCAD 2000: San Jose, California, USA
- Ellen Sentovich:
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000. IEEE Computer Society 2000, ISBN 0-7803-6448-1
Floorplanning and Partitioning
- Jason Cong, Sung Kyu Lim
:
Physical Planning with Retiming. 2-7 - Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. 8-12 - Florin Balasa:
Modeling Non-Slicing Floorplans with Binary Trees. 13-16 - Andrew B. Kahng, Stefanus Mantik:
On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools. 17-21
High Level Simulation
- Peter M. Maurer:
Event Driven Simulation Without Loops or Conditionals. 23-26 - José C. Costa, Srinivas Devadas, José Monteiro:
Observability Analysis of Embedded Software for Coverage-Directed Validation. 27-32 - Gernot Koch, Taewhan Kim, Reiner Genevriere:
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis. 33-38
Methods for DSP Synthesis and Debugging
- Farinaz Koushanfar, Darko Kirovski, Miodrag Potkonjak:
Symbolic Debugging Scheme for Optimized Hardware and Software. 40-43 - Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas:
Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering. 44-50 - Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park:
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. 51-54
Issues in Timing Estimation
- Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester:
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. 56-61 - Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu:
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. 62-67 - Pinhong Chen, Desmond Kirkpatrick, Kurt Keutzer:
Miller Factor for Gate-Level Coupling Delay Calculation. 68-74
Embedded Tutorial
- Jan M. Rabaey, Miodrag Potkonjak, Farinaz Koushanfar, Suet-Fei Li, Tim Tuan:
Challenges and Opportunities in Broadband and Wireless Communication Designs. 76-82
Embedded Tutorial
- Ralph H. J. M. Otten, Paul Stravers:
Challenges in Physical Chip Design. 84-91
Topics in Routing
- Hongbing Fan, Jiping Liu, Yu-Liang Wu:
General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs. 93-98 - Jiang Hu, Sachin S. Sapatnekar:
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. 99-103 - Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky:
Provably Good Global Buffering Using an Available Buffer Block Plan. 104-109 - Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh:
Predictable Routing. 110-113
Partial Verification Techniques
- Shankar G. Govindaraju, David L. Dill:
Counterexample-Guided Choice of Projections in Approximate Symbolic Model Checking. 115-119 - Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long:
Smart Simulation Using Collaborative Formal and Simulation Engines. 120-126 - C. Norris Ip:
Simulation Coverage Enhancement Using Test Stimulus Transformations. 127-133
Scheduling and Compilation for Embedded Systems
- Dirk Ziegenbein, Jan Uerpmann, Ralph Ernst:
Dynamic Response Time Optimization for SDF Graphs. 135-140
Inductance and Full-Wave Analysis
- Kenneth L. Shepard, Dipak Sitaram, Yu Zheng:
Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction. 142-149 - Anirudh Devgan, Hao Ji, Wayne Wei-Ming Dai:
How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K. 150-155 - Charlie Chung-Ping Chen, Tae-Woo Lee, Narayanan Murugesan, Susan C. Hagness:
Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling. 156-163
Placement I
- Sung-Woo Hur, John Lillis:
MONGREL: Hybrid Techniques for Standard Cell Placement. 165-170 - Tony F. Chan, Jason Cong, Tianming Kong, Joseph R. Shinnerl:
Multilevel Optimization for Large-Scale Circuit Placement. 171-176 - Fan Mo, Abdallah Tabbara, Robert K. Brayton:
A Force-Directed Macro-Cell Placer. 177-180
High-Level Design Tools for Analog Circuits
- Jeongjin Roh, Suresh Seshadri, Jacob A. Abraham:
Verification of Delta-Sigma Converters Using Adaptive Regression Modeling. 182-187 - Kenneth Francken, Peter J. Vancorenland, Georges G. E. Gielen:
DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators. 188-192 - Erik Lauwers, Georges G. E. Gielen:
ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters. 193-196
Delay Budgeting and Distribution
- Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh:
Potential Slack: An Effective Metric of Combinational Circuit Performance. 198-201 - Chien-Chu Kuo, Allen C.-H. Wu:
Delay Budgeting for a Timing-Closure-Driven Design Method. 202-207 - Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. 208-213
Interconnect Analysis
- Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi:
Hierarchical Interconnect Circuit Models. 215-221 - Xiaodong Yang, Chung-Kuan Cheng, Walter H. Ku, Robert J. Carragher:
Hurwitz Stable Reduced Order Modelling for RLC Interconnect Trees. 222-228 - Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan:
An "Effective" Capacitance Based Delay Metric for RC Interconnect. 229-234
Embedded Tutorial
- Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh:
Incremental CAD. 236-243
Embedded Tutorial
- Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani:
Decomposing Refinement Proofs Using Assume-Guarantee Reasoning. 245-252
Placement II
- Ke Zhong, Shantanu Dutt:
Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views. 254-259 - Maogang Wang, Xiaojian Yang, Majid Sarrafzadeh:
DRAGON2000: Standard-Cell Placement Tool for Large Industry Circuits. 260-263 - Terry Tao Ye, Giovanni De Micheli:
Data Path Placement with Regularity. 264-270
Analog and RF Simulation
- Baolin Yang, Dan Feng:
Efficient Finite-Difference Method for Quasi-Periodic Steady-State and Small Signal Analyses. 272-276 - Amit Mehrotra:
Noise Analysis of Phase-Locked Loops. 277-282 - Alper Demir, David E. Long, Jaijeet S. Roychowdhury:
Computing Phase Noise Eigenfunctions Directly from Steady-State Jacobian Matrices. 283-288
Markovian Analysis and Asynchronous Circuits
- Alper Demir, Peter Feldmann:
Modelling and Analysis of Communication Circuit Performance Using Markov Chains and Efficient Graph Representations. 290-295 - Sangyun Kim, Peter A. Beerel:
Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm. 296-302 - Hans M. Jacobson, Chris J. Myers, Ganesh Gopalakrishnan:
Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines. 303-310
Low Power Interconnect Modeling and Optimization
- Sungpack Hong, Taewhan Kim:
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method. 312-317 - Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang:
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. 318-321 - Paul-Peter Sotiriadis, Anantha P. Chandrakasan:
Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep Submicron Technologies. 322-327
Panel
- Andreas von Bechtolsheim, Joe Costello, Aart de Gues, Patrick Scaglia, Jennifer Smith:
Why Doesn't EDA Get Enough Respect? 329
Static Timing Analysis
- Pinhong Chen, Desmond Kirkpatrick, Kurt Keutzer:
Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise. 331-337 - David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda:
Slope Propagation in Static Timing Analysis. 338-343 - Pawan Kulshreshtha, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin:
Transistor-Level Timing Analysis Using Embedded Simulation. 344-348
Embedded Systems Power Management and Validation
- Dinesh Ramanathan, Sandy Irani, Rajesh K. Gupta:
Latency Effects of System Level Power Management Algorithms. 350-356 - Jiong Luo, Niraj K. Jha:
Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. 357-364 - Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai:
Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. 365-368 - Qiushuang Zhang, Ian G. Harris:
A Data Flow Fault Coverage Metric for Validation of Behavioral HDL Descriptions. 369-372
Advances in Layout and Synthesis
- Wei Chen, Cheng-Ta Hsieh, Massoud Pedram:
Simultaneous Gate Sizing and Fanout Optimization. 374-378 - Rajeev Murgai:
Layout-Driven Area-Constrained Timing Optimization by Net Buffering. 379-386 - Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang:
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. 387-390
Embedded Tutorial
- Yervant Zorian, Sujit Dey, Mike Rodgers:
Test of Future System-on-Chips. 392-398
Noise and Performance Issues in Routing
- Chung-Wen Albert Tsao, Cheng-Kok Koh:
UST/DME: A Clock Tree Router for General Skew Constraints. 400-405 - Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. 406-411 - Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. 412-418
Communication Architectures Design and Analysis
- Milenko Drinic, Darko Kirovski, Seapahn Meguerdichian, Miodrag Potkonjak:
Latency-Guided On-Chip Bus Network Design. 420-423 - Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Efficient Exploration of the SoC Communication Architecture Design Space. 424-430 - Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
MIST: An Algorithm for Memory Miss Traffic Management. 431-437
Performance Driven Logic Synthesis
- Thomas Kutzschebauch, Leon Stok:
Regularity Driven Logic Synthesis. 439-446 - Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh:
Timing Driven Gate Duplication: Complexity Issues and Algorithms. 447-450 - Arlindo L. Oliveira, Rajeev Murgai:
An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays. 451-457
New Approaches to At-Speed BIST and Diagnosis
- Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski:
Improving the Proportion of At-Speed Tests in Scan BIST. 459-463 - Seonki Kim, Bapiraju Vinnakota:
Fast Test Application Technique Without Fast Scan Clocks. 464-467 - Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu:
Error Catch and Analysis for Semiconductor Memories Using March Tests. 468-471 - Ian G. Harris, Russell Tessier:
Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures. 472-475
Power Analysis and Optimization
- Haihua Su, Kaushik Gala, Sachin S. Sapatnekar:
Fast Analysis and Optimization of Power/Ground Networks. 477-480 - Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
Simulation and Optimization of the Power Distribution Network in VLSI Circuits. 481-486 - Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Frequency Domain Analysis of Switching Noise on Power Supply Network. 487-492 - Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng:
Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. 493-496
VLIW Exploration and Design Synthesis
- Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria:
Power Exploration for Embedded VLIW Architectures. 498-503 - Margarida F. Jacome, Gustavo de Veciana, Viktor S. Lapinskii:
Exploring Performance Tradeoffs for Clustered VLIW ASIPs. 504-510 - James C. Hoe, Arvind:
Synthesis of Operation-Centric Hardware Descriptions. 511-518
Flexibility in Logic Synthesis
- Yunjian Jiang, Robert K. Brayton:
Don't Cares and Multi-Valued Logic Network Minimization. 520-525 - Victor N. Kravets, Karem A. Sakallah:
Generalized Symmetries in Boolean Functions. 526-532 - Shih-Chieh Chang, Zhong-Zhen Wu, He-Zhe Yu:
Wire Reconnections Based on Implication Flow Graph. 533-536
Digital and Analog Test Generation
- Ilker Hamzaoglu, Janak H. Patel:
Deterministic Test Pattern Generation Techniques for Sequential Circuits. 538-543 - Irith Pomeranz, Sudhakar M. Reddy:
Simulation Based Test Generation for Scan Designs. 544-549 - Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara:
Test Generation for Acyclic Sequential Circuits with Hold Registers. 550-556 - Michael Pronath, Volker Gloeckel, Helmut E. Graeb:
A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits. 557-561 - Sudip Chakrabarti, Abhijit Chatterjee:
Partial Simulation-Driven ATPG for Detection and Diagnosis of Faults in Analog Circuits. 562-567
Embedded Tutorial
- Lode Nachtergaele, Vivek Tiwari, Nikil D. Dutt:
System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media Applications. 569-573
Embedded Tutorial
- Andrzej J. Strojwas:
Design-Manufacturing Interface for 0.13 Micron and Below. 575
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