default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID17th FCCM 2009: Napa, CA, USA
- Kenneth L. Pocek, Duncan A. Buell:
FCCM 2009, 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, USA, 5-7 April 2009, Proceedings. IEEE Computer Society 2009, ISBN 978-0-7695-3716-0
Space and Scientific Applications
- Michael P. Caffrey, Keith Morgan
, Diane Roussel-Dupre, Scott Robinson, Anthony Nelson, Anthony Salazar, Michael J. Wirthlin, William Howes, Daniel Richins:
On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat). 3-10 - Volodymyr V. Kindratenko, Robert J. Brunner:
Accelerating Cosmological Data Analysis with FPGAs. 11-18 - Anthony E. Gregerson, Amin Farmahini Farahani, Ben Buchli, Steve Naumov, Michail Bachtis, Katherine Compton, Michael J. Schulte, Wesley H. Smith, Sridhara Dasu:
FPGA Design Analysis of the Clustering Algorithm for the CERN Large Hadron Collider. 19-26
High Speed Application Acceleration
- Anson H. T. Tse, David B. Thomas, Wayne Luk:
Accelerating Quadrature Methods for Option Valuation. 29-36 - Nachiket Kapre, André DeHon:
Accelerating SPICE Model-Evaluation using FPGAs. 37-44 - David B. Thomas, Wayne Luk:
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks. 45-52
Reconfiguration
- Suhaib A. Fahmy, Jorg Lotze, Juanjo Noguera, Linda Doyle, Robert Esser:
Generic Software Framework for Adaptive Applications on FPGAs. 55-62 - Kyle Rupnow, Wenyin Fu, Katherine Compton:
Block, Drop or Roll(back): Alternative Preemption Methods for RH Multi-Tasking. 63-70 - Amir Hossein Gholamipour, Hamid Eslami, Ahmed M. Eltawil, Fadi J. Kurdahi:
Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication Systems. 71-78
Search Applications
- Jin H. Park, Yunfei Qiu, Martin C. Herbordt:
CAAD BLASTP: NCBI BLASTP Accelerated with FPGA-Based Accelerated Pre-Filtering. 81-87 - Siddhartha Datta, Parag Beeraka, Ron Sass:
RC-BLASTn: Implementation and Evaluation of the BLASTn Scan Function. 88-95 - Qingbo Wang, Viktor K. Prasanna:
Multi-Core Architecture on FPGA for Large Dictionary String Matching. 96-103 - Yi-Hua Edward Yang, Viktor K. Prasanna:
Memory-Efficient Pipelined Architecture for Large-Scale String Matching. 104-111
Reconfigurable Architectures
- Srihari Cadambi, Igor Durdanovic, Venkata Jakkula, Murugan Sankaradass, Eric Cosatto, Srimat T. Chakradhar, Hans Peter Graf:
A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines. 115-122 - Deepak Unnikrishnan, Jia Zhao, Russell Tessier:
Application Specific Customization and Scalability of Soft Multiprocessors. 123-130 - Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen:
Benchmarking Reconfigurable Architectures in the Mobile Domain. 131-138
Image Processing
- Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis:
Optical Flow on the Ambric Massively Parallel Processor Array (MPPA). 141-148 - Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier:
Real-Time Fisheye Lens Distortion Correction Using Automatically Generated Streaming Accelerators. 149-156 - Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose:
FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. 157-164
Networking and Numerical Applications
- Hoang Le, Viktor K. Prasanna:
Scalable High Throughput and Power Efficient IP-Lookup on FPGA. 167-174 - Paul Edward McKechnie, Michaela Blott, Wim Vanderbauwhede:
Architectural Comparison of Instruments for Transaction Level Monitoring of FPGA-Based Packet Processing Systems. 175-182 - Guiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou, Miao Wang, Jingfei Jiang:
A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs. 183-190
Discrete Applications
- Samuel Antao, Ricardo Chaves, Leonel Sousa:
Compact and Flexible Microcoded Elliptic Curve Processor for Reconfigurable Devices. 193-200 - David DuBois, Andrew DuBois, Thomas Boorman, Carolyn Connor Davenport:
Non-Preconditioned Conjugate Gradient on Cell and FPGA Based Hybrid Supercomputer Nodes. 201-208 - Antonio Roldao Lopes, Amir Shahzad, George A. Constantinides, Eric C. Kerrigan:
More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control. 209-216
Short Papers
- Zachary K. Baker, Joshua S. Monson:
In-situ FPGA Debug Driven by On-Board Microcontroller. 219-222 - Jason D. Bakos, Krishna K. Nagar:
Exploiting Matrix Symmetry to Improve FPGA-Accelerated Conjugate Gradient. 223-226 - Jong-Ho Byun, Arun Ravindran, Arindam Mukherjee, Bharat Joshi, David Chassin:
Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer. 227-230 - Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Zhiru Zhang, Sheng Zhou, Yi Zou:
Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. 231-234 - G. Adam Covington, Glen Gibb, John W. Lockwood, Nick McKeown:
A Packet Generator on the NetFPGA Platform. 235-238 - Philip Garcia, Katherine Compton:
Shared Memory Cache Organizations for Reconfigurable Computing Systems. 239-242 - Rafael García, Ann Gordon-Ross, Alan D. George:
Exploiting Partially Reconfigurable FPGAs for Situation-Based Reconfiguration in Wireless Sensor Networks. 243-246 - Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Ghazawi:
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants. 247-250 - Dirk Koch, Christian Beckhoff, Jürgen Teich:
Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems. 251-254 - Holger Lange, Florian Stock, Andreas Koch, Dietmar Hildenbrand:
Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs. 255-258 - Martin Langhammer, Tom VanCourt:
FPGA Floating Point Datapath Compiler. 259-262 - Stephen Longfield Jr., Mark L. Chang:
A Parameterized Stereo Vision Core for FPGAs. 263-266 - Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne:
FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. 267-270 - Andrew G. Schmidt, William V. Kritikos, Rahul R. Sharma, Ron Sass:
AIREN: A Novel Integration of On-Chip and Off-Chip FPGA Networks. 271-274 - Tobias Schumacher, Christian Plessl, Marco Platzner:
IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. 275-278 - Joon Edward Sim, Weng-Fai Wong, Jürgen Teich:
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators. 279-282 - Margaret A. Sullivan, Herschel H. Loomis Jr., Alan A. Ross:
Employment of Reduced Precision Redundancy for Fault Tolerant FPGA Applications. 283-286 - Kostas Theocharoulis, Charalampos Manifavas, Ioannis Papaefstathiou:
High-End Reconfigurable Systems for Fast Windows' Password Cracking. 287-290 - Philip Top, Maya B. Gokhale:
Application Experiments: MPPA and FPGA. 291-294 - Chih-Hung Wu, Seda Ogrenci Memik, Sanjay Mehrotra:
FPGA Implementation of the Interior-Point Algorithm with Applications to Collision Detection. 295-298 - Jason Wu, John Williams, Neil W. Bergmann, Peter Sutton:
Design Exploration for FPGA-Based Multiprocessor Architecture: JPEG Encoding Case Study. 299-302 - Depeng Yang, Gregory D. Peterson, Husheng Li, Junqing Sun:
An FPGA Implementation for Solving Least Square Problem. 303-306
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-03-29 00:03 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
