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ORCID18th DAC 1981: Nashville, Tennessee, USA
- Robert J. Smith:
Proceedings of the 18th Design Automation Conference, DAC '81, Nashville, Tennessee, USA, June 29 - July 1, 1981. ACM/IEEE 1981 - Randolph Reitmeyer Jr.:
CAD for military systems, an essential link to LSI, VLSI and VHSIC technology. 3-12 - Charles M. Eastman:
Recent developments in representation in the science of design. 13-21 - G. Persky, C. Enger, D. M. Selove:
The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing. 22-28 - Xiong Ji-Guang, Tokinori Kozawa:
An algorithm for searching shortest path by propagating wave fronts in four quadrants. 29-36 - Hans-Jürgen Rothermel, Dieter A. Mlynski:
Computation of power supply nets in VLSI layout. 37-42 - Akihiko Yamada:
Design automation status in Japan. 43-50 - T. Hosaka, K. Ueda, H. Matsuura:
A design automation system for electronic switching systems. 51-58 - Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita:
An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2. 59-65 - R. A. Scoble:
Creating and updating space occupancy and building plans using interactive graphics. 66-73 - Plant design management system (PDMS) in action. 74
- Yehuda E. Kalay:
Interactive shape generation and spatial conflict testing. 75-81 - Wendell E. Cory:
Symbolic simulation for functional verification with ADLIB and SDL. 82-89 - Michael C. McFarland:
On proving the correctness of optimizing transformations in a digital design automation system. 90-97 - Hans Wojtkowiak:
Deterministic systems design from functional specifications. 98-104 - Tohru Sasaki, Akihiko Yamada, Toshinori Aoyama, Katsutoshi Hasegawa, Shunichi Kato, Shinichi Sato:
Hierarchical design verification for large digital systems. 105-112 - Adrian Hlynka:
A simulator to replace wire rules for high speed computer design. 113-117 - Ryotaro Kamikawai, Minoru Yamada, Tsuneyo Chiba, Kenichi Furumaya, Yoji Tsuchiya:
A critical path delay check system. 118-123 - Albert E. Ruehli:
Survey of analysis, simulation and modeling for large scale logic circuits. 124-129 - S. Aranoff, Y. Abulaffio:
Routing of printed circuit boards. 130-136 - Sheldon B. Akers Jr.:
On the use of the linear assignment algorithm in module placement. 137-144 - Charles F. Shupe:
Automatic component placement in an interactive minicomputer environment. 145-152 - Gotaro Odawara, Kazuhiko Iijima, Naoto Ichihara, Tetsuro Kiyomatsu:
PAS-LOP: An automatic module location system for PWB. 153-159 - Mike Mills:
A totally integrated systems approach to design and manufacturing at McDonnell Douglas Corporation. 160-165 - Gilbert W. Curl Jr.:
Mechanical design automation in IBM Poughkeepsie. 166-170 - D. L. Dewhirst, R. C. Hillyard:
Application of volumetric modeling to mechanical design and analysis. 171-178 - Y. K. Chan:
A perspective view of the MODCON system. 179-188 - Miron Abramovici:
A maximal resolution guided-probe testing algorithm. 189-195 - Vishwani D. Agrawal, Sharad C. Seth, Prathima Agrawal:
LSI product quality and fault coverage. 196-203 - Vijay Masurkar:
An algorithmic pretest development for fault identification in analog networks. 204-212 - Catherine Bellon, Gabriele Saucier, José-Maria Gobbi:
Hardware description levels and test for complex circuits. 213-219 - C. M. Lee, Basant R. Chawla, S. Just:
Automatic generation and characterization of CMOS polycells. 220-224 - Neil Weste:
Virtual grid symbolic layout. 225-233 - Stephen Trimberger:
Combining graphics and a layout language in a single interactive system. 234-239 - D. Franco, L. Reed:
The Cell Design System. 240-247 - S. Hirschhorn, M. Hommel, C. Bures:
Functional level simulation in FANSIM3 - algorithms, data structures and results. 248-255 - Susumu Goshima, Yuichi Oka, Tokinori Kozawa, Teruo Mori, Yoshimitsu Takeguchi, Yasuhiro Ohno:
Diagnostic system for large scale logic cards and LSI'S. 256-259 - Prabhakar Goel, Barry C. Rosales:
PODEM-X: An automatic test generation system for VLSI logic structures. 260-268 - Melvin A. Breuer, Alice C. Parker:
Digital system simulation: Current status and future trends or darwin's theory of simulation. 269-275 - Dan Holt, Steve Sapiro:
BOLT-a block oriented design specification language. 276-279 - Dan Holt, Dave Hutchings:
A MOS/LSI oriented logic simulator. 280-287 - Pauline Ng, Wolfram Glauert, Robert Kirk:
A timing verification system based on extracted MOS/VLSI circuit parameters. 288-292 - Chi-Song Horng, Margaret Lie:
An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks. 293-300 - Douglas W. Brown:
A State-Machine Synthesizer - SMS. 301-305 - Avinoam Bilgory, Daniel D. Gajski:
Automatic generation of cells for recurrence structures. 306-313 - Daniel E. Atkins, Wentai Liu, Shauchi Ong:
Overview of an Arithmetic Design System. 314-321 - Gary B. Goates, Suhas S. Patil:
ABLE: A LISP-based layout modeling language with user-definable procedural models for storage/logic array design. 322-329 - Ronald Waxman, Jonathan Allen, Robert W. Dutton, John M. Gould, Charles W. Gwyn, Paul Losleben, Dan C. Nash, Lawrence Sumney, H. Wayne Spence:
Government interest and involvement in design automation development (Panel Discussion). 330-331 - Jonathan Allen:
Government interest and involvement in design automation development (Position paper for the Panel Discussion). 332 - Robert W. Dutton:
Position statement - tools for design automation from a university point of view. 333 - John M. Gould:
Changing the Government's role in design automation (Position Paper). 334-335 - Charles W. Gwyn:
Government interest and involvement in DA from the Sandia viewpoint. 336 - Paul Losleben:
Current issues in government interest and involvement in CAD. 337-341 - Dan C. Nash:
Government actions to increase CAD software productivity. 342 - H. Wayne Spence:
Design Automation - a perspective (Position Paper). 343 - Larry W. Sumney:
Government interest and involvement in design automation development the VHSIC perspective. 344-346 - Yacoub M. El-Ziq:
Automatic test generation for stuck-open faults in CMOS VLSI. 347-354 - Paul M. Almy, Jose L. Rivero:
Using error latch trace to obtain diagnostic information. 355-359 - Robert M. McDermott:
Random fault analysis. 360-364 - H. Nelson Brady, Robert J. Smith:
Verification and optimization for LSI & PCB layout. 365-371 - Raymond Y. Tsui, Robert J. Smith:
A high-density multilayer PCB router based on necessary and sufficient conditions for single row routing. 372-381 - William A. Dees Jr., Robert J. Smith:
Performance of interconnection rip-up and reroute strategies. 382-390 - Sungho Kang, William M. van Cleemput:
Automatic PLA synthesis from a DDL-P description. 391-397 - I. Suwa, William J. Kubitz:
A computer-aided-design system for segmented-folded PLA macro-cells. 398-405 - Jean-François Paillotin:
Optimization of the PLA area. 406-410 - Arvind M. Patel, L. C. Cote:
Partitioning for VLSI placement problems. 411-418 - R. Malladi, Gilles Serrero, André Verdillon:
Automatic placement of rectangular blocks with the interconnection channels. 419-425 - K. H. Khokhani, Arvind M. Patel, W. Ferguson, J. Sessa, D. Hatton:
Placement of variable size circuits on LSI masterslices. 426-434 - G. Sakauye, Anna Lubiw, J. Royle, R. Epplett, Jeffrey Tweedale, E. S. Y. Shew, E. Attfield, Franc Brglez, Philip S. Wilcox:
A set of programs for MOS design. 435-442 - Gotaro Odawara, Satoshi Kurishima, Hiroshi Aoyama, Yasuhiko Kanaya:
PAS-CIP: An interactive logic design system. 443-450 - Takao Saito, Takao Uehara, Nobuaki Kawato:
A CAD system for logic design based on frames and demons. 451-456 - Robert C. Goldstein:
Defining the bounding edges of a SynthaVision solid model. 457-461 - William Luts:
Geometric modeling technology. 462 - Robert N. Wolfe, William J. Fitzgerald, Franklin Gracer:
Interactive graphics for volume modeling. 463-470 - Chia-Jeng Tseng, Daniel P. Siewiorek:
The modeling and synthesis of bus systems. 471-478 - Gary W. Leive, Donald E. Thomas:
A technology relative Logic Synthesis and Module Selection system. 479-485 - Andrew W. Nagle, Alice C. Parker:
Algorithms for multiple-criterion design of microprogrammed control hardware. 486-493 - Walter M. Anderson:
A multiprocessor raster display for interactive graphics system design. 494-497 - Frank R. Ramsay:
A remote design station for customer Uncommitted Logic Array designs. 498-504 - Tom H. Edmondson, Richard M. Jennings:
A low cost hierarchical system for VLSI layout and verification. 505-510 - Sany M. Leinwand:
Process oriented logic simulation. 511-517 - James R. Armstrong, D. E. Devlin:
GSP: A logic simulator for LSI. 518-524 - Howard E. Krohn:
Vector coding techniques for high speed digital simulation. 525-529 - Dan C. Nash, H. Willman:
Software engineering applied to computer-aided design (CAD) software development. 530-539 - Stanley Wong:
Computer-aided computer-aided design: Improving CAD programmer productivity. 540-545 - Carlo Batini, Maurizio Lenzerini:
INCOD: A system for Interactive Conceptual Data Base Design. 546-554 - Ulrich Lauther:
An O (N log N) algorithm for Boolean mask operations. 555-562 - Tokinori Kozawa, Akira Tsukizoe, Jun'ya Sakemi, Chihei Miura, Tatsuki Ishii:
A concurrent pattern operation algorithm for VLSI mask data. 563-570 - James A. Wilmore:
Efficient Boolean operations on IC masks. 571-579 - John McDermott:
Domain knowledge and the design process. 580-588 - Günther Zintl:
A CODASYL CAD data base system. 589-594 - Kenneth A. Roberts, Thomas E. Baker, David H. Jerome:
A vertically organized computer-aided design data base. 595-602 - Lance A. Glasser:
The analog behavior of digital integrated circuits. 603-612 - Paul Penfield Jr., Jorge Rubinstein:
Signal delay in RC tree networks. 613-617 - Harvey N. Lerman:
The generation of Technical Data Drawing Packages by the integration of Design Automation Graphics. 618-622 - Diana Mae Sims, James Crabbe:
User documentation for Design Automation at TI. 623-631 - Roger Cleghorn:
PRIMEAIDS: An integrated electrical design environment. 632-638 - Mitsuo Ishii, Yoshikazu Ito, Michiko Iwasaki, Masanari Yamamoto, Sadao Kodama:
Automatic input and interactive editing systems of logic circuit diagrams. 639-645 - Mark N. Haynie:
The relational/network Hybrid data model for Design Automation Databases. 646-652 - Michel Lacroix, Alain Pirotte:
Data structures for CAD object description. 653-659 - D. Wallace, L. Hemachandra:
Some properties of a probabilistic model for global wiring. 660-667 - J. Heinisch:
Aiming at a general routing strategy. 668-675 - William R. Heller:
Contrasts in physical design between LSI and VLSI. 676-683 - I. Ablasser, U. Jäger:
Circuit recognition and verification based on layout information. 684-689 - J. Yoshida, T. Ozaki, Y. Goto:
PANAMAP-B: A mask verification system for bipolar IC. 690-695 - L. V. Corbin:
Custom VLSI electrical rule checking in an intelligent terminal. 696-701 - R. I. McNall Jr., R. J. D'Innocenzo:
A structured approach to selecting a CAD/CAM system. 702 - Joseph Peled, Michael P. Carroll:
The "gap" between users and designers of CAD/CAM systems: Search for solutions. 703-705 - Peter E. Barck:
The role of engineering in the evolving technology/automation interface. 706-707 - Ed Burdick:
What to do when the seat of your pants wears out - the formalization of the VLSI design process. 708-709 - Paul Felton:
The effects of CAD on the engineering organization (Position paper). 710-711 - R. P. Lydick:
The role of engineering in the evolving technology/automation interface. 712 - David R. Lambert:
Graphics language / one - IBM Corporate-Wide physical design data format. 713-719 - Manfred A. Ward:
A total verification of printed circuit artwork. 720-725 - Laurin Williams:
Automatic VLSI layout verification. 726-732 - Maciej J. Ciesielski, Edwin Kinnen:
An optimum layer assignment for routing in ICs and PCBs. 733-737 - Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa:
On the layering problem of multilayer PWB wiring. 738-745 - Michel T. Doreau, Piotr Koziol:
TWIGY - a topological algorithm based routing system. 746-755 - Ming H. Young, Larry Cooke:
A preprocessor for channel routing. 756-761 - Michi M. Wada:
A dogleg "optimal" channel router with completion enhancements. 762-768 - Lai-Chering Suen:
A statistical model for net length estimation. 769-774 - Will Sherwood:
A MOS modelling technique for 4-state true-value hierarchical logic simulation or Karnough knowledge. 775-785 - Randal E. Bryant:
MOSSIM: A switch-level simulator for MOS LSI. 786-790 - Peter G. Raeth, John M. Acken, Gary B. Lamont, John M. Borky:
Functional modelling for logic simulation. 791-795 - D. J. Ellenberger, Ying W. Ng:
AIDE - a tool for computer architecture design. 796-803 - G. Martin, J. Berrie, T. Little, D. Mackay, J. McVean, D. Tomsett, L. Weston:
CELTIC - solving the problems of LSI design with an integrated polycell DA system. 804-811 - Chiyoji Tanaka, Shinichi Murai, Hiroo Tsuji, Toshihiko Yahara, Kaoru Okazaki, Masayuki Terai, Reiji Katoh, Mikio Tachibana:
An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3. 812-819 - Toru Chiba, Noboru Okuda, Takashi Kambe, Ikuo Nishioka, Tsuneo Inufushi, Sieji Kimura:
SHARPS: A hierarchical layout system for VLSI. 820-827 - Koji Sato, Takao Nagai, Mikio Tachibana, Hiroyoshi Shimoyama, Masaru Ozaki, Toshihiko Yahara:
MILD - A cell-based layout system for MOS-LSI. 828-836 - Tom Blank, Mark Stefik, William M. van Cleemput:
A parallel bit map processor architecture for DA algorithms. 837-845 - Louis J. Hafer, Alice C. Parker:
A formal method for the specification, analysis, and design of register-transfer level digital logic. 846-853 - Leonard Berman:
On logic comparison. 854-861 - Robert K. Montoye:
Area-time efficient addition in charge based technology. 862-872 - F. C. Bergsten:
Computer-Aided Design, Manufacturing, Assembly and Test (CADMAT). 873-880 - Peter Solecky, R. L. Panko:
Test data verification - not just the final step for test data before release for production testing. 881-890 - Frank C. Hsu, Peter Solecky, Robert E. Beaudoin:
Structured trace diagnosis for LSSD board testing - an alternative to full fault simulated diagnosis. 891-897
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