default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID10th AHS 2015: Montreal, QC, Canada
- 2015 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2015, Montreal, QC, Canada, June 15-18, 2015. IEEE 2015, ISBN 978-1-4673-7501-6
- Holger Michel, Adrian Belger, Tobias Lange, Björn Fiethe, Harald Michalik:
Read back scrubbing for SRAM FPGAs in a data processing unit for space instruments. 1-8 - Juan Pedro Cobos Carrascosa
, Beatriz Aparicio del Moral, Jose Luis Ramos Mas, María Balaguer, Antonio C. López Jiménez, J. C. del Toro Iniesta:
Scientific computing and fault mitigation on FPGA aboard the Solar Orbiter PHI instrument. 1-8 - Xabier Iturbe, Didier Keymeulen, Patrick Yiu, Dan Berisford, Kevin P. Hand, Robert Carlson, Emre Ozer:
Towards a generic and adaptive System-on-Chip controller for space exploration instrumentation. 1-8 - Alexander O. Erlank, Christopher P. Bridges:
A multicellular architecture towards low-cost satellite reliability. 1-8 - David Petrick, Nat Gill, Munther Hassouneh, Robert Stone, Luke Winternitz, Luke Thomas, Milton Davis, Pietro Sparacino, Thomas P. Flatley:
Adapting the SpaceCube v2.0 data processing system for mission-unique application requirements. 1-8 - Andreagiovanni Reina, Mattia Salvaro, Gianpiero Francesca, Lorenzo Garattoni, Carlo Pinciroli, Marco Dorigo, Mauro Birattari:
Augmented reality for robots: Virtual sensing technology applied to a swarm of e-pucks. 1-6 - Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau, Gregor Snelting:
Adaptive fault tolerance through invasive computing. 1-8 - Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Stephanie Friederich, Leonard Masing, Carsten Stein, Marco Duden, Roman Klopfer, Jürgen Teich, Thomas Wild, Andreas Herkersdorf, Jürgen Becker:
Fault-tolerant communication in invasive networks on chip. 1-8 - Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer:
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. 1-8 - Tobias Koal, Heinrich Theodor Vierhaus:
Redundancy evaluation process of processor components for permanent fault compensation. 1-6 - Robért Glein, Florian Rittner, Andreas Becher, Daniel Ziener, Jürgen Frickel, Jürgen Teich, Albert Heuberger:
Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy. 1-8 - Jorge L. Tonfat, Fernanda Lima Kastensmidt, Ricardo Reis:
Energy efficient frame-level redundancy scrubbing technique for SRAM-based FPGAs. 1-8 - Minoru Watanabe, Takumi Fujimori:
Holographic scrubbing technique for a programmable gate array. 1-5 - Daniel Ossmann, Franciscus L. J. van der Linden:
Advanced sensor fault detection and isolation for electro-mechanical flight actuators. 1-8 - Sara Zermani, Catherine Dezan, Reinhardt Euler, Jean-Philippe Diguet:
Bayesian network-based framework for the design of reconfigurable health management monitors. 1-8 - Dmitry Burlyaev, Pascal Fradet, Alain Girault:
Time-redundancy transformations for adaptive fault-tolerant circuits. 1-8 - Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre:
Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures. 1-8 - Dominique Blouin, Gilberto Ochoa-Ruiz, Yvan Eustache, Jean-Philippe Diguet:
Kaolin: A system-level AADL tool for FPGA design reuse, upgrade and migration. 1-8 - Himan Khanzadi, Yvon Savaria, Jean-Pierre David:
Mapping applications on two-level configurable hardware. 1-8 - Shervin Vakili, J. M. Pierre Langlois, Guy Bois:
Designing customized microprocessors for fixed-point computation. 1 - Kizheppatt Vipin, Suhaib A. Fahmy:
Mapping adaptive hardware systems with partial reconfiguration using CoPR for Zynq. 1-8 - Jalal Khalifat, Ali Ebrahim, Adewale Adetomi, Tughrul Arslan:
A dynamic partial reconfiguration design for camera systems. 1-7 - Mohammed Dali, Ryan M. Gibson, Abbes Amira, Abdelrezak Guessoum, Naeem Ramzan:
An efficient MIMO-OFDM radix-2 Single-Path Delay Feedback FFT implementation on FPGA. 1-7 - Giorgio C. Buttazzo, Luca Santinelli:
Adaptive mechanisms for component-based real-time systems. 1-8 - Anita Tino, Kaamran Raahemifar:
Addressing processor back-end issues with RCUs. 1-8 - Steven D. Pyle, Vignesh Thangavel, Stephen M. Williams, Ronald F. DeMara:
Self-Scaling Evolution of analog computation circuits with digital accuracy refinement. 1-8 - Jacopo Panerati, Giovanni Beltrame:
Trading off power and fault-tolerance in real-time embedded systems. 1-8 - Victor Dumitriu, Lev Kirischian, Valeri Kirischian:
Mitigation of variations in environmental conditions by SoPC architecture adaptation. 1-8 - Norma Montealegre, David Merodio, Agustín Fernández, Philippe Armbruster:
In-flight reconfigurable FPGA-based space systems. 1-8 - Nam Ho, Abdullah Fathi Ahmed, Paul Kaufmann, Marco Platzner:
Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. 1-7
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-03-01 15:19 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
