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ORCIDAlgorithmic Aspects of VLSI Layout, 1993
- Majid Sarrafzadeh, D. T. Lee:
Algorithmic Aspects of VLSI Layout. Lecture Notes Series on Computing 2, World Scientific 1993, ISBN 978-981-02-1488-3 - Malgorzata Marek-Sadowska:
Issues in Timing Driven Layout. 1-24 - S. M. Kang, M. Sriram:
Binary formulations for Placement and Routing Problems. 25-68 - Prithviraj Banerjee:
A Survey of Parallel Algorithms for VLSI cell Placement. 69-131 - Fillia Makedon, Spyros Tragoudas:
Approximate solutions for Graph and Hypergraph Partitioning. 133-166 - Thomas Lengauer, Martin Lügering:
Integer Program formulations of Global Routing and Placement Problems. 167-197 - Tetsuo Asano, Takeshi Tokuyama:
Circuit Partitioning Algorithms based on Geometry Model. 199-212 - Martin L. Brady, Donna J. Brown, Patrick J. McGuiness:
The three-dimensional channel Routing Problem. 213-244 - D. Zhou, Franco P. Preparata:
On the Manhattan and knock-knee Routing Models. 245-264 - Teofilo F. Gonzalez, Shashishekhar Kurki-Gowdara, Si-Qing Zheng:
Switch-Box Routing under the two-Overlap wiring Model. 265-308 - Ting-Chi Wang, D. F. Wong:
A note on the Complexity of Stockmeyer's floorplan Optimization Technique. 309-320 - Shuji Tsukiyama, Keiichi Koike, Isao Shirakawa:
An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan. 321-335 - Chuan-Jin Shi:
Constrained via Minimization and Signed Hypergraph Partitioning. 337-356 - Toshihiko Takahashi, Yoji Kajitani:
The Virtual Dimensions of a Straight Line Embedding of a plane Graph. 357-363 - Teofilo F. Gonzalez, Sing-Ling Lee:
Routing around two Rectangles to minimize the Layout Area. 365-397
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