dblp: Evaluating the efficiency of using TMR in the high-level synthesis design flow of SRAM-based FPGA.

"Evaluating the efficiency of using TMR in the high-level synthesis design ..."

André Flores dos Santos, Lucas Antunes Tambara, Fernanda Lima Kastensmidt (2017)

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DOI: 10.1109/LASCAS.2017.7948064

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

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