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ORCIDRicardo Augusto da Luz Reis
Ricardo A. L. Reis – Ricardo Reis 0001
Person information
- affiliation: Federal University of Rio Grande do Sul, Porto Alegre, Brazil
Other persons with the same name
- Ricardo Reis 0002
![[0000-0002-9103-4091]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-9103-4091")
— INESC TEC, Porto, Portugal
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2020 – today
- 2024
[c296]Rafael da Silva, Mateus Grellert, Ricardo Reis:
Energy-Efficient Design of Approximate VVC Interpolation Filters Units. ISVLSI 2024: 63-68- [c295]Alex Hanneman, Jonas Gava, Paulo Vancin, Aqsa Kk Kaim-Khani, Sam Amiri, Rafael Garibotti, Fernando Moraes, Ney Calazans, Ricardo Reis, Luciano Ost:
Soft Error Assessment of UAV Control Algorithms Running in Resource-Constrained Microprocessors. ISVLSI 2024: 694-698 - [c294]Geancarlo Abich, Ricardo Augusto da Luz Reis, Luciano Ost:
Early Soft Error Reliability Assessment of Convolutional Neural Networks Executing on Resource-constrained IoT Edge Devices. ITC 2024: 207-216 - [c293]Elias de Almeida Ramos, Ricardo Reis:
Comparing the Effects of Process Variability in FinFETs and CNFETs. LASCAS 2024: 1-5 - [c292]Luis Enrique Murillo Vizcardo, Ricardo Reis:
NEATRouter: A New Method for 2D Global Routing. VLSI-SoC 2024: 1-6 - 2023
- [j51]Leonardo Heitich Brendler, Hervé Lapuyade, Yann Deval, Frédéric Darracq, Frédéric Fauquet, Ricardo Reis, François Rivet:
A Proof-of-Concept of a Multiple-Cell Upsets Detection Method for SRAMs in Space Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4877-4887 (2023) - [c291]Leonardo Heitich Brendler, Hervé Lapuyade, Yann Deval, Ricardo Reis, François Rivet:
A Tool for Automatic Radiation-Hardened SRAM Layout Generation. ICECS 2023: 1-4 - [c290]Bernardo Borges Sandoval, Leonardo Heitich Brendler, Fernanda Lima Kastensmidt, Ricardo Reis, Alexandra L. Zimpeck, Rafael B. Schvittz, Cristina Meinhardt:
Impact on Radiation Robustness of Gate Mapping in FinFET Circuits under Work-function Fluctuation. ISCAS 2023: 1-5 - [c289]Geancarlo Abich, Anderson Ignacio da Silva, José Eduardo Thums, Rafael da Silva, Altamiro Amadeu Susin, Ricardo Reis, Luciano Ost:
Power, Performance and Reliability Evaluation of Multi-thread Machine Learning Inference Models Executing in Multicore Edge Devices. ISVLSI 2023: 1-6 - [c288]Leonardo Heitich Brendler, Hervé Lapuyade, Yann Deval, Ricardo Reis, François Rivet:
A MCU-robust Interleaved Data/Detection SRAM for Space Environments. ISVLSI 2023: 1-6 - [c287]Elias de Almeida Ramos, Ricardo Reis:
Using Lyapunov Exponents and Entropy to Estimate Sensitivity to Process Variability. ISVLSI 2023: 1-6 - [c286]Rodrigo N. Wuerdig, Vitor Hugo F. Maciel, Ricardo Reis, Sergio Bampi:
LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical Characterization. ISVLSI 2023: 1-6 - [c285]Elias de Almeida Ramos, Ricardo Reis:
Using Lyapunov Exponents to Estimate Sensitivity to Process Variability. LASCAS 2023: 1-4 - [c284]Geancarlo Abich, Anderson Ignacio da Silva, Jonas Gava, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis, Luciano Ost:
Power and Performance Costs of Radiation-Hardened ML Inference Models Running on Edge Devices. SBCCI 2023: 1-6 - [c283]Rafael da Silva, Mateus Grellert, Ricardo Reis:
An Energy-Efficient Interpolation Unit Targeting VVC Encoders with Approximate Adder. SBCCI 2023: 1-5 - [c282]Alex Hanneman, Jonas Gava, Vitor V. Bandeira, Rafael Garibotti, Ricardo Reis, Luciano Ost:
DeBaTE-FI: A Debugger-Based Fault Injector Infrastructure for IoT Soft Error Reliability Assessment. WF-IoT 2023: 1-6 - 2022
- [j50]Fábio G. R. G. da Silva, Rafael N. M. Oliveira, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis:
Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology. Integr. 87: 137-146 (2022) - [j49]Jonas Gava, Vitor V. Bandeira, Felipe Rosa, Rafael Garibotti, Ricardo Reis, Luciano Ost:
SOFIA: An automated framework for early soft error assessment, identification, and mitigation. J. Syst. Archit. 131: 102710 (2022) - [j48]Geancarlo Abich, Rafael Garibotti, Ricardo Reis, Luciano Ost:
The Impact of Soft Errors in Memory Units of Edge Devices Executing Convolutional Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 679-683 (2022) - [c281]Jonas Gava, Guilherme Dorneles, Ricardo Reis, Rafael Garibotti, Luciano Ost:
Soft Error Assessment of CNN Inference Models Running on a RISC-V Processor. ICECS 2022 2022: 1-4 - [c280]Ricardo Reis:
Research Experience as a Way to Improve Retention and Graduation Rates. ISCAS 2022: 110-113 - [c279]Vinícius Da Rocha, Nicolas Moura, Jonas Gava, Vitor V. Bandeira, Luciano Ost, Ricardo Augusto da Luz Reis, Rafael Garibotti:
Soft Error Reliability Assessment of Lightweight Cryptographic Algorithms for IoT Edge Devices. ISCAS 2022: 457-460 - [c278]Ricardo Augusto da Luz Reis:
A Lifetime of Physical Design Automation and EDA Education: ISPD 2022 Lifetime Achievement Award Bio. ISPD 2022: 137-138 - [c277]Ricardo Augusto da Luz Reis:
Physical Design Optimization, From Past to Future. ISPD 2022: 145-148 - [c276]Geancarlo Abich, Rafael Garibotti, Jonas Gava, Ricardo Reis, Luciano Ost:
Impact of Thread Parallelism on the Soft Error Reliability of Convolution Neural Networks. LASCAS 2022: 1-4 - [c275]Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis, Rafael B. Schvittz, Cristina Meinhardt:
Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing. SBCCI 2022: 1-6 - [c274]Jonas Gava, Ricardo Reis, Luciano Ost:
Investigation of Hybrid Soft Error Mitigation Techniques for Applications running on Resource-constrained devices. VLSI-SoC 2022: 1-2 - [e23]Victor Grimblatt, Chip-Hong Chang, Ricardo Reis, Anupam Chattopadhyay, Andrea Calimera:
VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 661, Springer 2022, ISBN 978-3-031-16817-8 [contents] - 2021
- [j47]Geancarlo Abich, Rafael Garibotti, Vitor V. Bandeira, Felipe da Rosa, Jonas Gava, Felipe T. Bortolon, Guilherme Medeiros, Fernando Moraes, Ricardo Reis, Luciano Ost:
Evaluation of the soft error assessment consistency of a JIT-based virtual platform simulator. IET Comput. Digit. Tech. 15(2): 125-142 (2021) - [j46]Geancarlo Abich, Jonas Gava, Rafael Garibotti, Ricardo Reis, Luciano Ost:
Applying Lightweight Soft Error Mitigation Techniques to Embedded Mixed Precision Deep Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4772-4782 (2021) - [j45]Vitor V. Bandeira, Isadora Oliveira, Felipe Rosa, Ricardo Reis, Luciano Ost:
An Extensive Soft Error Reliability Analysis of a Real Autonomous Vehicle Software Stack. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 446-450 (2021) - [c273]Gerson D. Andrade, Ricardo A. L. Reis, Eduardo A. C. da Costa, Alexandra L. Zimpeck:
Sensitivity of FinFET Adders to PVT Variations and Sleep Transistor as a Mitigation Strategy. APCCAS 2021: 37-40 - [c272]Geancarlo Abich, Ricardo Reis, Luciano Ost:
The Impact of Precision Bitwidth on the Soft Error Reliability of the MobileNet Network. LASCAS 2021: 1-4 - [c271]Leonardo Heitich Brendler, Alexandra L. Zimpeck, Fernanda Lima Kastensmidt, Cristina Meinhardt, Ricardo A. L. Reis:
Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit. LASCAS 2021: 1-4 - [c270]Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis:
Current Behavior on Process Variability Aware FinFET Inverter Designs. LASCAS 2021: 1-4 - [c269]Isadora Oliveira, Marcelo Danigno, Paulo F. Butzen, Ricardo Reis:
Benchmarking Open Access VLSI Partitioning Tools. LASCAS 2021: 1-4 - [c268]Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis, Cristina Meinhardt:
SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology. LATS 2021: 1-2 - [c267]Bernardo Borges Sandoval, Leonardo Heitich Brendler, Alexandra L. Zimpeck, Fernanda Lima Kastensmidt, Ricardo Reis, Cristina Meinhardt:
Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study. LATS 2021: 1-6 - [c266]Vitor Hugo F. Maciel, Germano Girondi, Elias de Almeida Ramos, Ricardo Reis:
Exploring a New Tool for Automatic Layout Synthesis for FDSOI 28 nm. VLSI-SoC 2021: 1-2 - [e22]Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis:
VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 621, Springer 2021, ISBN 978-3-030-81640-7 [contents] - 2020
- [b1]Felipe Rocha da Rosa, Luciano Ost, Ricardo Reis:
Soft Error Reliability Using Virtual Platforms - Early Evaluation of Multicore Systems. Springer 2020, ISBN 978-3-030-55703-4, pp. 1-136 - [j44]Mateus Fogaça, Andrew B. Kahng, Eder Monteiro, Ricardo Reis, Lutong Wang, Mingyu Woo:
On the superiority of modularity-based clustering for determining placement-relevant clusters. Integr. 74: 32-44 (2020) - [j43]Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(2): 553-564 (2020) - [c265]Daiane Freitas, Rafael da Silva, Ícaro Siqueira, Cláudio Machado Diniz, Ricardo A. L. Reis, Mateus Grellert:
Hardware Architecture for the Regular Interpolation Filter of the AV1 Video Coding Standard. EUSIPCO 2020: 560-564 - [c264]Mateus Fogaça, Eder Monteiro, Marcelo Danigno, Isadora Oliveira, Paulo F. Butzen, Ricardo Reis:
Contributions to OpenROAD from Abroad: Experiences and Learnings : Invited Paper. ICCAD 2020: 113:1-113:8 - [c263]Geancarlo Abich, Jonas Gava, Ricardo Reis, Luciano Ost:
Soft Error Reliability Assessment of Neural Networks on Resource-constrained IoT Devices. ICECS 2020: 1-4 - [c262]Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis, Cristina Meinhardt:
Mirror Full Adder SET Susceptibility on 7nm FinFET Technology. ICECS 2020: 1-4 - [c261]Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis:
Pros and Cons of ST and SIG FinFET Inverters for Low Power Designs. ISCAS 2020: 1-5 - [c260]Juliano C. Zanelli, Carolina Metzler, Ricardo Augusto da Luz Reis:
Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits. LASCAS 2020: 1-4 - [c259]Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters. LATS 2020: 1-6 - [c258]Ricardo A. L. Reis, Cristina Meinhardt, Alexandra L. Zimpeck, Leonardo Heitich Brendler, Leonardo B. Moraes:
Circuit Level Design Methods to Mitigate Soft Errors. LATS 2020: 1-3 - [c257]Fabio G. Rossato G. da Silva, Cristina Meinhardt, Ricardo Reis:
Mitigation Effects of Decoupling Cells on Full Adders Process Variability. MWSCAS 2020: 317-320 - [c256]Vitor V. Bandeira, Mateus Fogaça, Eder Matheus Monteiro, Isadora Oliveira, Mingyu Woo, Ricardo Augusto da Luz Reis:
Fast and Scalable I/O Pin Assignment with Divide-and-Conquer and Hungarian Matching. NEWCAS 2020: 74-77 - [c255]Jonas Gava, Ricardo Augusto da Luz Reis, Luciano Ost:
RAT: A Lightweight System-level Soft Error Mitigation Technique. VLSI-SOC 2020: 165-170 - [c254]Jonas Gava, Ricardo Reis, Luciano Ost:
RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique. VLSI-SoC (Selected Papers) 2020: 235-253 - [c253]Calebe Micael de Oliveira Conceição, Ricardo Augusto da Luz Reis:
Security Issues in the Design of Chips for IoT. WF-IoT 2020: 1-5 - [e21]Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva Cárdenas, Ricardo Reis:
VLSI-SoC: New Technology Enabler - 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6-9, 2019, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 586, Springer 2020, ISBN 978-3-030-53272-7 [contents]
2010 – 2019
- 2019
- [j42]Rafael Garibotti, Luciano Ost, Anastasiia Butko, Ricardo Reis, Abdoulaye Gamatié, Gilles Sassatelli:
Exploiting memory allocations in clusterised many-core architectures. IET Comput. Digit. Tech. 13(4): 302-311 (2019) - [j41]Felipe Rocha da Rosa, Rafael Garibotti, Luciano Ost, Ricardo Reis:
Using Machine Learning Techniques to Evaluate Multicore Soft Error Reliability. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2151-2164 (2019) - [j40]Elias de Almeida Ramos, Guilherme Bontorin, Ricardo Reis:
A New Nonlinear Global Placement for FPGAs: The Chaotic Place. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2165-2174 (2019) - [j39]Calebe Micael de Oliveira Conceição, Ricardo Augusto da Luz Reis:
Transistor Count Reduction by Gate Merging. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2175-2187 (2019) - [c252]Mateus Fogaça, Andrew B. Kahng, Ricardo Reis, Lutong Wang:
Finding placement-relevant clusters with fast modularity-based clustering. ASP-DAC 2019: 569-576 - [c251]Jorge Ferreira, Paulo F. Butzen, Cristina Meinhardt, Ricardo A. L. Reis:
FBM: A Simple and Fast Algorithm for Placement Legalization. ICECS 2019: 209-212 - [c250]Alexandra L. Zimpeck, Cristina Meinhardt, Laurent Artola, Guillaume Hubert, Fernanda Lima Kastensmidt, Ricardo Augusto da Luz Reis:
Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility. ICECS 2019: 582-585 - [c249]Marcelo Danigno, Paulo F. Butzen, Jorge Ferreira, André Oliveira, Eder Monteiro, Mateus Fogaça, Ricardo Augusto da Luz Reis:
Proposal and Evaluation of Pin Access Algorithms for Detailed Routing. ICECS 2019: 602-605 - [c248]Fabio G. Rossato G. da Silva, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
FinFET Variability and Near-threshold operation: Impact on Full Adders design using XOR Blocks. ICECS 2019: 638-641 - [c247]Ricardo Reis:
Challenges in the Design of Integrated Systems for IoT. IFIPIoT 2019: 179-196 - [c246]Jonas Gava, Vitor V. Bandeira, Ricardo Reis, Luciano Ost:
Evaluation of Compilers Effects on OpenMP Soft Error Resiliency. ISVLSI 2019: 259-264 - [c245]Henrique Placido, Ricardo Reis:
Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm. ISVLSI 2019: 284-289 - [c244]Samuel Presa Toledo, Ricardo Reis, Cristina Meinhardt:
Process Variability Challenges for Radiation Mitigation Techniques on 16nm. LASCAS 2019: 69-72 - [c243]Andre Saldanha Oliveira, Julia Casarin Puget, Carolina Metzler, Ricardo Reis:
Clip Clustering for Early Lithographic Hotspot Classification. LASCAS 2019: 149-152 - [c242]Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Exploring Schmitt Trigger Circuits for Process Variability Mitigation. NEWCAS 2019: 1-4 - [c241]Elias de Almeida Ramos, João Carlos Britto Filho, Ricardo A. L. Reis:
Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body. NEWCAS 2019: 1-4 - [c240]Leonardo B. Moraes, Alexandra Lackmann Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis:
Robust FinFET Schmitt Trigger Designs for Low Power Applications. VLSI-SoC (Selected Papers) 2019: 45-68 - [c239]Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability. VLSI-SoC 2019: 88-93 - [c238]Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis:
Process Variability Impact on the SET Response of FinFET Multi-level Design. VLSI-SoC (Selected Papers) 2019: 89-113 - [c237]Vitor V. Bandeira, Felipe Rosa, Ricardo Reis, Luciano Ost:
Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques. VLSI-SoC (Selected Papers) 2019: 115-137 - [c236]Vitor V. Bandeira, Felipe Rosa, Ricardo Augusto da Luz Reis, Luciano Ost:
Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability Analysis. VLSI-SoC 2019: 123-128 - [c235]Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis:
Evaluation of SET under Process Variability on FinFET Multi-level Design. VLSI-SoC 2019: 179-184 - [c234]Calebe Micael de Oliveira Conceição, Ricardo Augusto da Luz Reis:
Netlist Optimization by Gate Merging. VLSI-SoC 2019: 236-237 - [c233]Alexandra L. Zimpeck, Cristina Meinhardt, Laurent Artola, Guillaume Hubert, Fernanda Lima Kastensmidt, Ricardo Augusto da Luz Reis:
Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs. VLSI-SoC 2019: 240-241 - [c232]Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Robustness and Minimum Energy-Oriented FinFET Design. VLSI-SoC 2019: 247-248 - [c231]Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis:
Impact of Process Variability and Single Event Transient on FinFET Technology. VLSI-SoC 2019: 249-250 - [c230]Isadora Oliveira, Vitor V. Bandeira, Ricardo A. L. Reis, Luciano Ost:
Exploration of Techniques to Assess Soft Errors in Multicore Architectures. VLSI-SoC 2019: 251-252 - [c229]Vitor V. Bandeira, Isadora Oliveira, Felipe da Rosa, Ricardo A. L. Reis, Luciano Ost:
Soft Error Reliability Analysis of Autonomous Vehicles Software Stack. VLSI-SoC 2019: 253-254 - [c228]Kevin A. Cáceres Albinagorta, Calebe Conceição, Carlos Silva Cárdenas, Ricardo A. L. Reis:
Exploring area and total wirelength using a cell merging technique. VLSI-SoC 2019: 329-334 - [e20]Michail Maniatakos, Ibrahim Abe M. Elfadel, Matteo Sonza Reorda, H. Fatih Ugurdag, José Monteiro, Ricardo Reis:
VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 500, Springer 2019, ISBN 978-3-030-15662-6 [contents] - [e19]Nicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd M. Austin, Ricardo Reis:
VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 561, Springer 2019, ISBN 978-3-030-23424-9 [contents] - 2018
- [j38]Alexandra L. Zimpeck, Cristina Meinhardt, Laurent Artola, Guillaume Hubert, Fernanda Lima Kastensmidt, Ricardo Augusto da Luz Reis:
Impact of different transistor arrangements on gate variability. Microelectron. Reliab. 88-90: 111-115 (2018) - [j37]Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Evaluation of variability using Schmitt trigger on full adders layout. Microelectron. Reliab. 88-90: 116-121 (2018) - [j36]Roberto B. Almeida, Cleiton Magano Marques, Paulo F. Butzen, Fábio G. R. G. da Silva, Ricardo A. L. Reis, Cristina Meinhardt:
Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies. Microelectron. Reliab. 88-90: 196-202 (2018) - [c227]Felipe da Rosa, Vitor V. Bandeira, Ricardo Reis, Luciano Ost:
Extensive evaluation of programming models and ISAs impact on multicore soft error reliability. DAC 2018: 178:1-178:6 - [c226]Fabio G. Rossato G. da Silva, Cristina Meinhardt, Ricardo Reis:
Impact of Near-Threshold and Variability on 7nm FinFET XOR Circuits. ICECS 2018: 573-576 - [c225]Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis:
Exploring Multi-level Design to Mitigate Variability and Radiation Effects on 7nm FinFET Logic Cells. ICECS 2018: 581-584 - [c224]Ricardo Reis:
Strategies for Reducing Power Consumption and Increasing Reliability in IoT. IFIPIoT@WCC 2018: 76-88 - [c223]Felipe T. Bortolon, Geancarlo Abich, Sergio Bampi, Ricardo Reis, Fernando Moraes, Luciano Ost:
Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems. ISCAS 2018: 1-5 - [c222]Samuel Presa Toledo, Alexandra L. Zimpeck, Ricardo Reis, Cristina Meinhardt:
Pros and Cons of Schmitt Trigger Inverters to Mitigate PVT Variability on Full Adders. ISCAS 2018: 1-5 - [c221]Lucas de Paris, Ricardo Reis:
An automated methodology to fix electromigration violations on a customized design flow. LASCAS 2018: 1-4 - [c220]Elias de Almeida Ramos, Guilherme Bontorin, Ricardo Reis:
A nonlinear placement for FPGAs: The chaotic place. LASCAS 2018: 1-4 - [c219]Felipe Rocha da Rosa, Ricardo Reis, Luciano Ost:
gem5-FIM: a flexible and scalable multicore soft error assessment framework to early reliability design space explorations. LASCAS 2018: 1-4 - [c218]Luciana Mendes da Silva, Guilherme Bontorin, Ricardo Reis:
Reducing the amount of transistors by gate merging. LASCAS 2018: 1-4 - [c217]Jean Carlo Hamerski, Geancarlo Abich, Ricardo Reis, Luciano Ost, Alexandre M. Amory:
A Design Patterns-Based Middleware for Multiprocessor Systems-on-Chip. SBCCI 2018: 1-6 - [c216]Guilherme E. Medeiros, Felipe T. Bortolon, Ricardo Reis, Luciano Ost:
Evaluation of Compiler Optimization Flags Effects on Soft Error Resiliency. SBCCI 2018: 1-6 - [c215]Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis:
Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements. VLSI-SoC 2018: 71-76 - 2017
- [j35]Walter E. Calienes Bartra, Y. Q. de Aguiar, Cristina Meinhardt, Andrei Vladimirescu, Ricardo Augusto da Luz Reis:
Evaluation of heavy-ion impact in bulk and FDSOI devices under ZTC condition. Microelectron. Reliab. 76-77: 655-659 (2017) - [j34]Y. Q. de Aguiar, Laurent Artola, Guillaume Hubert, Cristina Meinhardt, Fernanda Lima Kastensmidt, Ricardo Augusto da Luz Reis:
Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology. Microelectron. Reliab. 76-77: 660-664 (2017) - [c214]Julia Casarin Puget, Andre Saldanha Oliveira, Jorge Seelen, Ricardo Reis:
UFRGSPlace: Routability driven FPGA placement algorithm for heterogeneous FPGAs. ICECS 2017: 38-41 - [c213]Calebe Conceição, Gisell Moura, Filipe Pisoni, Ricardo Reis:
A cell clustering technique to reduce transistor count. ICECS 2017: 186-189 - [c212]Ygor Q. Aguiar, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis:
Temperature dependence and ZTC bias point evaluation of sub 20nm bulk multigate devices. ICECS 2017: 270-273 - [c211]Y. Q. de Aguiar, Fernanda Lima Kastensmidt, Cristina Meinhardt, Ricardo A. L. Reis:
SET response of FinFET-based majority voter circuits under work-function fluctuation. ICECS 2017: 282-285 - [c210]Samuel Presa Toledo, Alexandra L. Zimpeck, Ricardo Reis, Cristina Meinhardt:
Impact of schmitt trigger inverters on process variability robustness of 1-Bit full adders. ICECS 2017: 290-293 - [c209]Gennaro Severino Rodrigues, Felipe Rosa, Fernanda Lima Kastensmidt, Ricardo Reis, Luciano Ost:
Investigating parallel TMR approaches and thread disposability in Linux. ICECS 2017: 393-396 - [c208]Jean Carlo Hamerski, Geancarlo Abich, Ricardo Reis, Luciano Ost, Alexandre M. Amory:
Publish-subscribe programming for a NoC-based multiprocessor system-on-chip. ISCAS 2017: 1-4 - [c207]Alexandra L. Zimpeck, Ygor Aguiar, Cristina Meinhardt, Ricardo Reis:
Robustness of Sub-22nm multigate devices against physical variability. ISCAS 2017: 1-4 - [c206]Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
Rsyn: An Extensible Physical Synthesis Framework. ISPD 2017: 33-40 - [c205]Ygor Q. de Aguiar, Cristina Meinhardt, Ricardo A. L. Reis:
Radiation sensitivity of XOR topologies in multigate technologies under voltage variability. LASCAS 2017: 1-4 - [c204]Walter E. Calienes Bartra, Andrei Vladimirescu, Ricardo Reis:
Process and temperature impact on single-event transients in 28nm FDSOI CMOS. LASCAS 2017: 1-4 - [c203]Felipe Rosa, Luciano Ost, Ricardo Reis, Simon Davidmann, Larry Lapides:
Evaluation of multicore systems soft error reliability using virtual platforms. NEWCAS 2017: 85-88 - [c202]Ricardo Reis, Manfred Glesner:
VLSI-SoC: An Enduring Tradition. VLSI-SoC (Selected Papers) 2017: 240-255 - [e18]Thomas Hollstein, Jaan Raik, Sergei Kostin, Anton Tsertov, Ian O'Connor, Ricardo Reis:
VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability - 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers. IFIP Advances in Information and Communication Technology 508, Springer 2017, ISBN 978-3-319-67103-1 [contents] - 2016
- [j33]Tiago Reimann, Cliff C. N. Sze, Ricardo Reis:
Challenges of cell selection algorithms in industrial high performance microprocessor designs. Integr. 52: 347-354 (2016) - [j32]Ricardo Reis, Nadine Azémard:
Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1-4, 2015. J. Low Power Electron. 12(1): 56-57 (2016) - [j31]Y. Q. de Aguiar, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Permanent and single event transient faults reliability evaluation EDA tool. Microelectron. Reliab. 64: 63-67 (2016) - [j30]Walter E. Calienes Bartra, Andrei Vladimirescu, Ricardo Augusto da Luz Reis:
FDSOI and Bulk CMOS SRAM Cell Resilience to Radiation Effects. Microelectron. Reliab. 64: 152-157 (2016) - [j29]Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar:
Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2): 220-231 (2016) - [c201]Alexandra L. Zimpeck, Ygor Aguiar, Cristina Meinhardt, Ricardo Reis:
Geometric variability impact on 7nm Trigate combinational cells. ICECS 2016: 9-12 - [c200]Priscila C. Holanda, Cezar R. W. Reinbrecht, Guilherme Bontorin, Vitor V. Bandeira, Ricardo A. L. Reis:
DHyANA: A NoC-based neural network hardware architecture. ICECS 2016: 177-180 - [c199]Alexandra L. Zimpeck, Ricardo Reis:
Impact of variability effects on FinFET transistors and combinational cells. ICECS 2016: 440-441 - [c198]Mateus Fogaça, Guilherme Flach, Jucemar Monteiro, Marcelo O. Johann, Ricardo Reis:
Quadratic timing objectives for incremental timing-driven placement optimization. ICECS 2016: 620-623 - [c197]Geancarlo Abich, Marcelo G. Mandelli, Felipe R. Rosa, Fernando Gehm Moraes, Luciano Ost, Ricardo Reis:
Extending FreeRTOS to support dynamic and distributed mapping in multiprocessor systems. ICECS 2016: 712-715 - [c196]Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Augusto da Luz Reis:
FinFET cells with different transistor sizing techniques against PVT variations. ISCAS 2016: 45-48 - [c195]Lucas de Paris, Gracieli Posser, Ricardo Reis:
Electromigration aware circuits by using special signal non-default routing rules. ISCAS 2016: 2795-2798 - [c194]Tiago J. Reimann, Cliff C. N. Sze, Ricardo Reis:
Cell Selection for High-Performance Designs in an Industrial Design Flow. ISPD 2016: 65-72 - [c193]Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
Drive Strength Aware Cell Movement Techniques for Timing Driven Placement. ISPD 2016: 73-80 - [c192]Jucemar Monteiro, Nima Karimpour Darav, Guilherme Flach, Mateus Fogaça, Ricardo Augusto da Luz Reis, Andrew A. Kennings, Marcelo O. Johann, Laleh Behjat:
Routing-Aware Incremental Timing-Driven Placement. ISVLSI 2016: 290-295 - [c191]Calebe Conceição, Gracieli Posser, Ricardo Reis:
Reducing the number of transistors with gate clustering. LASCAS 2016: 163-166 - [c190]Mateus Fogaça, Guilherme Flach, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
Improving placement algorithms by using visualization tools. NEWCAS 2016: 1-4 - [c189]Jorge L. Tonfat, Guilherme Flach, Ricardo Reis:
Leakage current analysis in static CMOS logic gates for a transistor network design approach. PATMOS 2016: 107-113 - [e17]Youngsoo Shin, Chi-Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis:
VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers. IFIP Advances in Information and Communication Technology 483, Springer 2016, ISBN 978-3-319-46096-3 [contents] - 2015
- [j28]Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Impact of PVT variability on 20 nm FinFET standard cells. Microelectron. Reliab. 55(9-10): 1379-1383 (2015) - [j27]Felipe Rosa, Raphael Martins Brum, Gilson I. Wirth, Fernanda Gusmão de Lima Kastensmidt, Luciano Ost, Ricardo Reis:
Impact of dynamic voltage scaling and thermal factors on SRAM reliability. Microelectron. Reliab. 55(9-10): 1486-1490 (2015) - [c188]Cristiano Santos, Rafael Prieto, Pascal Vivet, Jean-Philippe Colonna, Perceval Coudrain, Ricardo Reis:
Graphite-based heat spreaders for hotspot mitigation in 3D ICs. 3DIC 2015: TS10.4.1-TS10.4.4 - [c187]Jorge L. Tonfat, Fernanda Lima Kastensmidt, Ricardo Reis:
Energy efficient frame-level redundancy scrubbing technique for SRAM-based FPGAs. AHS 2015: 1-8 - [c186]Tiago Reimann, Cliff C. N. Sze, Ricardo Reis:
Gate sizing and threshold voltage assignment for high performance microprocessor designs. ASP-DAC 2015: 214-219 - [c185]Felipe Rosa, Fernanda Lima Kastensmidt, Ricardo Reis, Luciano Ost:
A fast and scalable fault injection framework to evaluate multi/many-core soft error reliability. DFTS 2015: 211-214 - [c184]Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Reis:
Process variability in FinFET standard cells with different transistor sizing techniques. ICECS 2015: 121-124 - [c183]Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar:
Impact on performance, power, area and wirelength using electromigration-aware cells. ICECS 2015: 129-132 - [c182]Walter E. Calienes Bartra, Andrei Vladimirescu, Ricardo Reis:
Bulk and FDSOI Sub-micron CMOS transistors resilience to single-event transients. ICECS 2015: 133-136 - [c181]Felipe Rosa, Raphael Martins Brum, Gilson I. Wirth, Luciano Ost, Ricardo Reis:
Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability. ICECS 2015: 137-140 - [c180]Vitor V. Bandeira, Vivianne L. Costa, Guilherme Bontorin, Ricardo A. L. Reis:
Low Latency FPGA Implementation of Izhikevich-Neuron Model. IESS 2015: 210-217 - [c179]Daniel S. Guimarães Jr., Julia Casarin Puget, Ricardo Augusto da Luz Reis:
A mixed cells physical design approach. ISCAS 2015: 1446-1449 - [c178]Alexandra L. Zimpeck, Fernanda Lima Kastensmidt, Ricardo Reis:
Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops. ISVLSI 2015: 521-526 - [c177]Walter E. Calienes Bartra, Ricardo Reis, Andrei Vladimirescu:
Modeling the impact of heavy ion on FDSOI NanoCMOS. LASCAS 2015: 1-4 - [c176]Calebe Conceição, Ricardo Reis:
Efficient emulation of quantum circuits on classical hardware. LASCAS 2015: 1-4 - [c175]Gracieli Posser, Lucas de Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar:
Reducing the signal Electromigration effects on different logic gates by cell layout optimization. LASCAS 2015: 1-4 - [c174]Diego Tumelero, Guilherme Bontorin, Ricardo Reis:
Overhead for independent net approach for Global Routing. LASCAS 2015: 1-4 - [c173]Jimmy Tarrillo, Jorge L. Tonfat, Lucas A. Tambara, Fernanda Lima Kastensmidt, Ricardo Reis:
Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments. LATS 2015: 1-6 - [c172]Roger Caputo-Llanos, Diego Sousa, Marco Terres, Guilherme Bontorin, Ricardo Reis, Marcelo O. Johann:
Energy-efficient Level Shifter topology. PATMOS 2015: 148-151 - [c171]Sidinei Ghissoni, Eduardo Costa, Ricardo Reis:
Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs. PATMOS 2015: 169-176 - [c170]Julia Casarin Puget, Guilherme Flach, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
Jezz: An Effective Legalization Algorithm for Minimum Displacement. SBCCI 2015: 19:1-19:5 - [c169]Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
An Incremental Timing-Driven flow using quadratic formulation for detailed placement. VLSI-SoC 2015: 1-6 - [e16]Alex Orailoglu, H. Fatih Ugurdag, Luís Miguel Silveira, Martin Margala, Ricardo Reis:
VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 461, Springer 2015, ISBN 978-3-319-23798-5 [contents] - [e15]Luc Claesen, María Teresa Sanz-Pascual, Ricardo Reis, Arturo Sarmiento-Reyes:
VLSI-SoC: Internet of Things Foundations - 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 464, Springer 2015, ISBN 978-3-319-25278-0 [contents] - 2014
- [j26]Cristina Meinhardt, Alexandra L. Zimpeck, Ricardo A. L. Reis:
Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations. Microelectron. Reliab. 54(9-10): 2319-2324 (2014) - [j25]Fernanda Lima Kastensmidt, Jorge L. Tonfat, Thiago Hanna Both, Paolo Rech, Gilson I. Wirth, Ricardo Reis, Florent Bruguier, Pascal Benoit, Lionel Torres, Christopher Frost:
Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs. Microelectron. Reliab. 54(9-10): 2344-2348 (2014) - [j24]Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis:
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 546-557 (2014) - [c168]Cristiano Santos, Papa Momar Souare, François de Crecy, Perceval Coudrain, Jean-Philippe Colonna, Pascal Vivet, Andras Borbely, Ricardo Reis, M. Haykel Ben Jamaa, Vincent Fiori, Alexis Farcy:
Using TSVs for thermal mitigation in 3D circuits: Wish and truth. 3DIC 2014: 1-8 - [c167]Cristiano Santos, Pascal Vivet, Jean-Philippe Colonna, Perceval Coudrain, Ricardo Augusto da Luz Reis:
Thermal performance of 3D ICs: Analysis and alternatives. 3DIC 2014: 1-7 - [c166]Cristiano Santos, Pascal Vivet, Gene Matter, Nicolas Peltier, Sylvian Kaiser, Ricardo Augusto da Luz Reis:
Thermal modeling methodology for efficient system-level thermal analysis. CICC 2014: 1-4 - [c165]Fernanda Lima Kastensmidt, Jorge L. Tonfat, Thiago Hanna Both, Paolo Rech, Gilson I. Wirth, Ricardo Reis, Florent Bruguier, Pascal Benoit, Lionel Torres, Christopher Frost:
Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs. ETS 2014: 1-2 - [c164]Adriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans:
A design flow for physical synthesis of digital cells with ASTRAN. ACM Great Lakes Symposium on VLSI 2014: 245-246 - [c163]Tania Mara Ferla, Guilherme Flach, Ricardo Reis:
A tool to simulate optical lithography in nanoCMOs. I2MTC 2014: 1471-1474 - [c162]Walter E. Calienes Bartra, Ricardo Reis:
A set of Virtual Instruments to simulate radiation effects in CMOS circuits. I2MTC 2014: 1643-1646 - [c161]Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar:
A systematic approach for analyzing and optimizing cell-internal signal electromigration. ICCAD 2014: 486-491 - [c160]Cristina Meinhardt, Alexandra L. Zimpeck, Ricardo Augusto da Luz Reis:
Impact of gate workfunction fluctuation on FinFET standard cells. ICECS 2014: 574-577 - [c159]Gracieli Posser, Vivek Mishra, Ricardo Augusto da Luz Reis, Sachin S. Sapatnekar:
Analyzing the electromigration effects on different metal layers and different wire lengths. ICECS 2014: 682-685 - [c158]Cristiano Santos, Pascal Vivet, Ricardo Augusto da Luz Reis:
Thermal impact of 3D stacking and die thickness: Analysis and characterization of a memory-on-logic 3D circuit. ICECS 2014: 718-721 - [c157]Adriel Mota Ziesemer, Ricardo Augusto da Luz Reis:
Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN. ISVLSI 2014: 350-355 - [c156]Gracieli Posser, Jozeanne Belomo, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices. ISVLSI 2014: 418-423 - [c155]Cristina Meinhardt, Ricardo Reis:
Comparing high-performance cells in CMOS bulk and FinFET technologies. LASCAS 2014: 1-4 - [c154]Marco Terres, Cristina Meinhardt, Guilherme Bontorin, Ricardo Reis:
Exploring more efficient architectures for Multiple Dynamic Supply Voltage designs. LASCAS 2014: 1-4 - [c153]Adriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans:
Automatic layout synthesis with ASTRAN applied to asynchronous cells. LASCAS 2014: 1-4 - [c152]Lucas A. Tambara, Jorge L. Tonfat, Ricardo Reis, Fernanda Lima Kastensmidt, Evaldo Carlos Fonseca Pereira, Rafael Galhardo Vaz, Odair Lelis Goncalez:
Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects. LATW 2014: 1-6 - [c151]Walter E. Calienes Bartra, Ricardo Augusto da Luz Reis, Costin Anghel, Andrei Vladimirescu:
Bulk and FDSOI SRAM resiliency to radiation effects. MWSCAS 2014: 655-658 - [c150]Felipe Rosa, Luciano Ost, Thiago Raupp da Rosa, Fernando Gehm Moraes, Ricardo Reis:
Fast energy evaluation of embedded applications for many-core systems. PATMOS 2014: 1-6 - [c149]Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis:
Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices. PATMOS 2014: 1-8 - [c148]Matheus Trevisan, Michel Evandro Arendt, Adriel Ziesemer, Ricardo Augusto da Luz Reis, Ney Laert Vilar Calazans:
Automated Synthesis of Cell Libraries for Asynchronous Circuits. SBCCI 2014: 16:1-16:7 - [c147]Giovanni Bruni, Paolo Rech, Lucas A. Tambara, Gabriel L. Nazar, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis, Alessandro Paccagnella:
Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity. VLSI-SoC 2014: 1-6 - 2013
- [j23]Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis:
Revisiting automated physical synthesis of high-performance clock networks. ACM Trans. Design Autom. Electr. Syst. 18(2): 31:1-31:27 (2013) - [c146]Cristiano Santos, Pascal Vivet, Denis Dutoit, Philippe Garrault, Nicolas Peltier, Ricardo Reis:
System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit. 3DIC 2013: 1-6 - [c145]Anelise Kologeski, Caroline Concatto, Debora Matos, Daniel Grehs, Tiago Motta, Felipe Almeida, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Ricardo Reis:
Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip. ICECS 2013: 125-128 - [c144]Marco Terres, Cristina Meinhardt, Guilherme Bontorin, Ricardo Reis:
A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage. ICECS 2013: 715-718 - [c143]Felipe Rosa, Luciano Ost, Ricardo Reis, Gilles Sassatelli:
Instruction-driven timing CPU model for efficient embedded software development using OVP. ICECS 2013: 855-858 - [c142]Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis:
Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing. ISCAS 2013: 2549-2552 - [c141]Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis:
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. ISVLSI 2013: 84-89 - [c140]Fernanda Lima Kastensmidt, Ricardo Reis, Leandro Soares Indrusiak, Gilles Sassatelli:
Message from the general and program chairs. ISVLSI 2013 - [c139]Jimmy Tarrillo, Jorge L. Tonfat, Fernanda Lima Kastensmidt, Ricardo Reis, Florent Bruguier, Morgan Bourree, Pascal Benoit, Lionel Torres:
Using electromagnetic emanations for variability characterization in Flash-based FPGAs. ISVLSI 2013: 109-114 - [c138]Cristina Meinhardt, Ricardo Reis:
A yield-driven regular layout synthesis. ISVLSI 2013: 221-222 - [c137]Cristina Meinhardt, Ricardo Reis:
FinFET basic cells evaluation for regular layouts. LASCAS 2013: 1-4 - [c136]Leandro Nunes, Ricardo Reis:
Global routing congestion reduction with cost allocation look-ahead. SBCCI 2013: 1-5 - [c135]Leandro Nunes, Tiago Reimann, Ricardo Reis:
GR-PA: A cost pre-allocation model for global routing. VLSI-SoC 2013: 134-137 - [e14]Andreas Burg, Ayse K. Coskun, Matthew R. Guthaus, Srinivas Katkoori, Ricardo Reis:
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers. IFIP Advances in Information and Communication Technology 418, Springer 2013, ISBN 978-3-642-45072-3 [contents] - [e13]Martin Margala, Ricardo Augusto da Luz Reis, Alex Orailoglu, Luigi Carro, Luís Miguel Silveira, H. Fatih Ugurdag:
21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013. IEEE 2013, ISBN 978-1-4799-0522-5 [contents] - 2012
- [j22]Renato Fernandes Hentschke, Marcelo O. Johann, Ricardo Reis:
Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias. RITA 19(1): 28-45 (2012) - [j21]Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis:
High-performance clock mesh optimization. ACM Trans. Design Autom. Electr. Syst. 17(3): 33:1-33:17 (2012) - [c134]Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis:
Efficient area and power multiplication part of FFT based on twiddle factor decomposition. ICECS 2012: 657-660 - [c133]Raul Chipana, Eduardo Chielle, Fernanda Lima Kastensmidt, Jorge L. Tonfat, Ricardo Reis:
Soft-Error Probability Due to SET in Clock Tree Networks. ISVLSI 2012: 338-343 - [c132]Walter E. Calienes Bartra, Fernanda Lima Kastensmidt, Ricardo Reis:
Simulation of SET faults in a voltage controlled oscillator. LATW 2012: 1-6 - [c131]Raul Chipana, Fernanda Lima Kastensmidt, Jorge L. Tonfat, Ricardo Reis:
SET susceptibility estimation of clock tree networks from layout extraction. LATW 2012: 1-6 - [c130]Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis:
Transistor sizing and gate sizing using geometric programming considering delay minimization. NEWCAS 2012: 85-88 - [c129]Cristiano Santos, Ricardo Reis, Guilherme Godoi, Marcos Barros, Fabio Duarte:
Multi-bit flip-flop usage impact on physical synthesis. SBCCI 2012: 1-6 - [e12]José L. Ayala, David Atienza Alonso, Ricardo Reis:
VLSI-SoC: Forward-Looking Trends in IC and Systems Design - 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers. IFIP Advances in Information and Communication Technology 373, Springer 2012, ISBN 978-3-642-28565-3 [contents] - [e11]Salvador Mir, Chi-Ying Tsui, Ricardo Reis, Oliver C. S. Choy:
VLSI-SoC: Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected Papers. IFIP Advances in Information and Communication Technology 379, Springer 2012, ISBN 978-3-642-32769-8 [contents] - [e10]Srinivas Katkoori, Matthew R. Guthaus, Ayse K. Coskun, Andreas Burg, Ricardo Reis:
20th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012. IEEE 2012, ISBN 978-1-4673-2657-5 [contents] - 2011
- [j20]Massimo Violante, Cristina Meinhardt, Ricardo Reis, Matteo Sonza Reorda:
A Low-Cost Solution for Deploying Processor Cores in Harsh Environments. IEEE Trans. Ind. Electron. 58(7): 2617-2626 (2011) - [c128]Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis:
Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization. ICECS 2011: 567-570 - [c127]Gerson Scartezzini, Ricardo Reis:
Power consumption in transistor networks versus in standard cells. ICECS 2011: 740-743 - [c126]Ricardo Reis:
Design automation of transistor networks, a new challenge. ISCAS 2011: 2485-2488 - [c125]Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis:
Gate Sizing Minimizing Delay and Area. ISVLSI 2011: 315-316 - [c124]Jorge L. Tonfat, Gustavo Neuberger, Ricardo Reis:
Functional verification of logic modules for a Gigabit Ethernet switch. LATW 2011: 1-4 - [c123]Guilherme Flach, Marcelo O. Johann, Ricardo Reis:
Quadratic placement with single-iteration linear system solver. SBCCI 2011: 109-112 - [p1]Ricardo Reis:
Design Tools and Methods for Chip Physical Design. Multiprocessor System-on-Chip 2011: 155-166 - [e9]Jürgen Becker, Marcelo O. Johann, Ricardo Reis:
VLSI-SoC: Technologies for Systems Integration - 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil, October 12-14, 2009, Revised Selected Papers. IFIP Advances in Information and Communication Technology 360, Springer 2011, ISBN 978-3-642-23119-3 [contents] - 2010
- [j19]Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis:
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits. CLEI Electron. J. 13(3) (2010) - [j18]Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis:
Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies. Microelectron. Reliab. 50(9-11): 1241-1246 (2010) - [c122]Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis:
Non-uniform clock mesh optimization with linear programming buffer insertion. DAC 2010: 74-79 - [c121]Glauco Borges Valim dos Santos, Tiago Reimann, Marcelo O. Johann, Ricardo Reis:
The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms. ICCD 2010: 195-202 - [c120]Jorge L. Tonfat, Ricardo Reis:
Design and verification of a layer-2 Ethernet MAC classification engine for a Gigabit Ethernet switch. ICECS 2010: 146-149 - [c119]Tiago Reimann, Glauco B. V. dos Santos, Ricardo A. L. Reis:
Routing algorithms performance in different routing scopes. ICECS 2010: 643-646 - [c118]Gracieli Posser, Adriel Ziesemer, Daniel Guimares Jr., Gustavo Wilke, Ricardo A. L. Reis:
A study on layout quality of automatic generated cells. ICECS 2010: 651-654 - [c117]Sidinei Ghissoni, Eduardo Costa, Cristiano Lazzari, José Monteiro, Levent Aksoy, Ricardo Reis:
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. ICECS 2010: 859-862 - [c116]Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira:
Predictive error detection by on-line aging monitoring. IOLTS 2010: 9-14 - [c115]Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis:
Evaluating transient-fault effects on traditional C-element's implementations. IOLTS 2010: 35-40 - [c114]Felipe Pinto, Lucas Cavalheiro, Marcelo O. Johann, Ricardo Reis:
Logical Core Algorithm: Improving Global Placement. ISVLSI 2010: 69-73 - [c113]Guilherme Flach, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis:
A Mesh-Buffer Displacement Optimization Strategy. ISVLSI 2010: 282-287 - [c112]Gustavo Wilke, Ricardo Reis:
Variability-aware physical design techniques. LATW 2010: 1 - [c111]Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel Maria Cacho Teixeira, Marcelino B. Santos, João Paulo Teixeira:
Low-sensitivity to process variations aging sensor for automotive safety-critical applications. VTS 2010: 238-243 - [e8]Christian Piguet, Ricardo Reis, Dimitrios Soudris:
VLSI-SoC: Design Methodologies for SoC and SiP - 16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, Rhodes Island, Greece, October 13-15, 2008, Revised Selected Papers. IFIP Advances in Information and Communication Technology 313, Springer 2010, ISBN 978-3-642-12266-8 [contents]
2000 – 2009
- 2009
- [j17]Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis:
Design of a soft-error robust microprocessor. Microelectron. J. 40(7): 1062-1068 (2009) - [j16]Renato Fernandes Hentschke, Jagannathan Narasimhan, Marcelo O. Johann, Ricardo Reis:
Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1073-1086 (2009) - [c110]Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis:
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. DATE 2009: 352-357 - [c109]Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis:
An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. DFT 2009: 254-262 - [c108]Cristiano Lazzari, Adriel Ziesemer, Ricardo Reis:
An automated design methodology for layout generation targeting power leakage minimization. ICECS 2009: 81-84 - [c107]Glauco B. V. dos Santos, Tiago Reimann, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis:
On the accuracy of Elmore-based Delay Models. ICECS 2009: 447-450 - [c106]Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis:
A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits. ICECS 2009: 852-855 - [c105]Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira:
Built-in aging monitoring for safety-critical applications. IOLTS 2009: 9-14 - [c104]Rodrigo Possamai Bastos, Yannick Monnet, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis:
Comparing transient-fault effects on synchronous and on asynchronous circuits. IOLTS 2009: 29-34 - [c103]Thiago Assis, Fernanda Lima Kastensmidt, Gilson I. Wirth, Ricardo Reis:
Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies. LATW 2009: 1-6 - [c102]Cristina Meinhardt, Ricardo Reis, Massimo Violante, Matteo Sonza Reorda:
Recovery scheme for hardening system on programmable chips. LATW 2009: 1-6 - [c101]Sidinei Ghissoni, João Baptista dos Santos Martins, Ricardo Augusto da Luz Reis, José C. Monteiro:
Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates. PATMOS 2009: 297-306 - [c100]Érika F. Cota, Luigi Carro, Felipe Pinto, Ricardo Augusto da Luz Reis, Marcelo Lubaszewski:
Resource-and-time-aware test strategy for configurable quaternary logic blocks. SBCCI 2009 - [c99]Gustavo Neuberger, Gilson I. Wirth, Ricardo Reis:
Protecting digital circuits against hold time violation due to process variability. SBCCI 2009 - [c98]Sergio Bampi, Ricardo Reis:
Challenges and Emerging Technologies for System Integration beyond the End of the Roadmap of Nano-CMOS. VLSI-SoC 2009: 21-33 - 2008
- [j15]Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis:
Probabilistic Approach for Yield Analysis of Dynamic Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(8): 2238-2248 (2008) - [c97]Pasquale Delizia, Marcello De Matteis, Stefano D'Amico, Andrea Baschirotto, Carlos Azeredo Leme, Ricardo Reis:
Design procedure for DVB-T receivers large tuning range LP filter. ISCAS 2008: 2913-2916 - [c96]Gustavo Wilke, Ricardo Reis:
A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction. ISVLSI 2008: 227-232 - [c95]Gustavo Wilke, Renan Fonseca, Cecilia Mezzomo, Ricardo Reis:
A novel scheme to reduce short-circuit power in mesh-based clock architectures. SBCCI 2008: 117-122 - 2007
- [j14]Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara, Luigi Carro, Ricardo Reis, Xavier Guerin, Ahmed Amine Jerraya:
Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC. Des. Autom. Embed. Syst. 11(4): 249-283 (2007) - [j13]Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel:
A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis. J. Electron. Test. 23(6): 625-633 (2007) - [j12]Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo Augusto da Luz Reis:
Técnicas probabilísticas para análise de yield em nível elétrico usando propagação de erros e derivadas numéricas. RITA 14(2): 69-89 (2007) - [j11]Leandro Soares Indrusiak, Manfred Glesner, Ricardo Reis:
On the Evolution of Remote Laboratories for Prototyping Digital Electronic Systems. IEEE Trans. Ind. Electron. 54(6): 3069-3077 (2007) - [c94]José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Ricardo Reis, Manfred Glesner:
Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes. ICECS 2007: 1007-1010 - [c93]Cristina Meinhardt, Ricardo Reis, Reginaldo Tavares:
Logic and Physical Synthesis of Cell Arrays. ICECS 2007: 1292-1295 - [c92]Renato Fernandes Hentschke, Ricardo Reis:
A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length. ISCAS 2007: 2036-2039 - [c91]Renato Fernandes Hentschke, Jaganathan Narasimham, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
Maze routing steiner trees with effective critical sink optimization. ISPD 2007: 135-142 - [c90]Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis:
3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. ISVLSI 2007: 67-72 - [c89]Lucas Brusamarello, Roberto da Silva, Ricardo A. L. Reis, Gilson I. Wirth:
Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations. ISVLSI 2007: 86-91 - [c88]José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis:
Inserting Data Encoding Techniques into NoC-Based Systems. ISVLSI 2007: 299-304 - [c87]Reginaldo Tavares, William Lautenschlager, Ricardo Reis:
A CAL Tool to Aid the Understanding of Logic Synthesis. MSE 2007: 49-50 - [c86]Adriel Ziesemer, Cristiano Lazzari, Ricardo Reis:
An Educational Tool for Design Automation of CMOS Cells. MSE 2007: 149-150 - [c85]Guilherme Flach, Marcelo O. Johann, Renato Fernandes Hentschke, Ricardo Reis:
Cell placement on graphics processing units. SBCCI 2007: 87-92 - [c84]Lisane B. de Brisolara, Sang-Il Han, Xavier Guerin, Luigi Carro, Ricardo Reis, Soo-Ik Chae, Ahmed Amine Jerraya:
Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC. SCOPES 2007: 81-89 - [c83]Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo Reis:
Statistical and Numerical Approach for a Computer efficient circuit yield analysis. VLSI-SoC (Selected Papers) 2007: 1-24 - [c82]Gustavo Neuberger, Gilson I. Wirth, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis:
Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies. VLSI-SoC (Selected Papers) 2007: 1-16 - [c81]Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis, Gilson I. Wirth, Ralf Brederlow, Christian Pacha:
Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies. VLSI-SoC 2007: 78-83 - [c80]Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis:
Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level. VLSI-SoC 2007: 94-98 - [c79]Cristiano Lazzari, Cristiano Santos, Adriel Ziesemer, Lorena Anghel, Ricardo Reis:
Efficient timing closure with a transistor level design flow. VLSI-SoC 2007: 312-315 - [e7]Ricardo Augusto da Luz Reis, Adam Osseiran, Hans-Jörg Pfleiderer:
VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia. IFIP 240, Springer 2007, ISBN 978-0-387-73660-0 [contents] - [e6]Giovanni De Micheli, Salvador Mir, Ricardo Reis:
VLSI-SoC: Research Trends in VLSI and Systems on Chip - Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France. IFIP 249, Springer 2007, ISBN 978-0-387-74908-2 [contents] - 2006
- [c78]Sandro Sawicki, Renato Fernandes Hentschke, Marcelo O. Johann, Ricardo Reis:
Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits. ICECS 2006: 399-402 - [c77]Cristiano Lazzari, Cristiano Santos, Ricardo Reis:
A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits. ICECS 2006: 660-663 - [c76]Reginaldo Tavares, Cristina Meinhardt, Ricardo Reis:
orBDDs Direct Mapping for Structured Logic Circuits. ICECS 2006: 1057-1060 - [c75]Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel:
Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study. IOLTS 2006: 165-172 - [c74]Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis:
Design of a Robust 8-Bit Microprocessor to Soft Errors. IOLTS 2006: 195-196 - [c73]Glauco Borges Valim dos Santos, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis:
Channel based routing in channel-less circuits. ISCAS 2006 - [c72]Claudio Menezes, Cristina Meinhardt, Ricardo Reis, Reginaldo Tavares:
A Regular Layout Approach for ASICs. ISVLSI 2006: 424-425 - [c71]José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes:
Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. ISVLSI 2006: 426-427 - [c70]Daniel Lima Ferrão, Ricardo Reis, José Luís Almada Güntzel:
Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis. PATMOS 2006: 301-310 - [c69]José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis:
Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. PATMOS 2006: 603-613 - [c68]Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis:
Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates. SBCCI 2006: 196-201 - [c67]Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis:
Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. SBCCI 2006: 220-225 - [c66]Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias. VLSI-SoC 2006: 128-133 - [c65]Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Reis:
A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits. VLSI-SoC (Selected Papers) 2006: 259-279 - [e5]Manfred Glesner, Ricardo Augusto da Luz Reis, Leandro Soares Indrusiak, Vincent John Mooney III, Hans Eveking:
VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany. IFIP 200, Springer 2006, ISBN 978-0-387-33402-8 [contents] - 2005
- [j10]Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis:
An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories. IEEE Des. Test Comput. 22(1): 50-58 (2005) - [j9]Fernanda Lima Kastensmidt, Gustavo Neuberger, Luigi Carro, Ricardo Reis:
Desenvolvimento de Técnicas de Tolerância à Falhas para Componentes Programáveis por SRAM. RITA 12(1): 47-60 (2005) - [c64]Lisane B. de Brisolara, Leandro Buss Becker, Luigi Carro, Flávio Rech Wagner, Carlos Eduardo Pereira, Ricardo Reis:
Comparing high-level modeling approaches for embedded system design. ASP-DAC 2005: 986-989 - [c63]Gustavo Neuberger, Fernanda Lima Kastensmidt, Ricardo Reis:
TOC-BISR: A Self-Repair Scheme for Memories in Embedded Systems. IESS 2005: 157-168 - [c62]Renato Fernandes Hentschke, Marcelo O. Johann, Ricardo Reis:
Blue Macaw: A Didactic Placement Tool Using Simulated Annealing. EDUTECH 2005: 37-47 - [c61]Cristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis:
On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study. IOLTS 2005: 29-34 - [c60]Cristiano Santos, Daniel Lima Ferrão, Ricardo Reis, José Luís Güntzel:
Incremental timing optimization for automatic layout generation. ISCAS (4) 2005: 3567-3570 - [c59]Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis:
Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory. PATMOS 2005: 59-68 - [c58]José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin:
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. SBCCI 2005: 196-201 - [c57]Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José Monteiro, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis:
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. VLSI-SoC 2005: 25-39 - [c56]César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis:
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. VLSI-SoC 2005: 179-194 - [c55]Cristiano Lazzari, Lorena Anghel, Ricardo Reis:
A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming. VLSI-SoC 2005: 331-344 - 2004
- [j8]Fernanda Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis:
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs. IEEE Des. Test Comput. 21(6): 552-562 (2004) - [j7]Leandro Soares Indrusiak, Ricardo A. L. Reis, Manfred Glesner:
Um Framework de Apoio à Colaboração no Projeto Distribuído de Sistemas Integrados. RITA 11(2): 49-74 (2004) - [c54]Ricardo Reis, Fernanda Lima Kastensmidt, José Luís Almada Güntzel:
Physical design methodologies for performance predictability and manufacturability. Conf. Computing Frontiers 2004: 390-397 - [c53]Fernanda Lima Kastensmidt, Gustavo Neuberger, Luigi Carro, Ricardo Reis:
Designing and testing fault-tolerant techniques for SRAM-based FPGAs. Conf. Computing Frontiers 2004: 419-432 - [c52]Alex Panato, Sandro V. Silva, Flávio Rech Wagner, Marcelo O. Johann, Ricardo Reis, Sergio Bampi:
Design of Very Deep Pipelined Multipliers for FPGAs. DATE 2004: 52-57 - [c51]Ricardo Reis:
Requirements for Computer-Aided Learning from the Point of View of Electronic Design. EDUTECH 2004: 63-68 - [c50]Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis:
A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. PATMOS 2004: 732-741 - [c49]Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis:
Accurate capture of timing parameters in inductively-coupled on-chip interconnects. SBCCI 2004: 117-122 - [c48]Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis:
Lookup-based Remote Laboratory for FPGA Digital Design Prototyping. VIRTUAL-LAB 2004: 3-11 - [e4]Ricardo Reis:
Information Technology, Selected Tutorials, IFIP 18th World Computer Congress, Tutorials, 22-27 August 2004, Toulouse, France. IFIP 157, Kluwer/Springer 2004, ISBN 1-4020-8158-8 [contents] - 2003
- [j6]Kong-Pang Pun, José E. da Franca, Carlos Azeredo Leme, Ricardo Reis:
Quadrature sampling schemes with improved image rejection. IEEE Trans. Circuits Syst. II Express Briefs 50(9): 641-648 (2003) - [j5]Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro, Ricardo Augusto da Luz Reis:
A multiple bit upset tolerant SRAM memory. ACM Trans. Design Autom. Electr. Syst. 8(4): 577-590 (2003) - [c47]Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz Reis:
Designing fault tolerant systems into SRAM-based FPGAs. DAC 2003: 650-655 - [c46]Leandro Soares Indrusiak, Florian Lubitz, Ricardo Augusto da Luz Reis, Manfred Glesner:
Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues. DATE 2003: 10940-10945 - [c45]Alex Panato, Marcelo Barcelos, Ricardo Augusto da Luz Reis:
A Low Device Occupation IP to Implement Rijndael Algorithm. DATE 2003: 20020-20025 - [c44]Leandro Soares Indrusiak, Ricardo Reis, Manfred Glesner:
Supporting Consistency Control between Functional and Structural Views in Interface-based Design Models. FDL 2003: 364-373 - [c43]Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz Reis:
Reducing pin and area overhead in fault-tolerant FPGA-based designs. FPGA 2003: 108-117 - [c42]Renato Fernandes Hentschke, Ricardo Reis:
Plic-Plac: a novel constructive algorithm for placement. ISCAS (5) 2003: 461-464 - [c41]Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis, Giuliana Alcántara, Stefan Hoermann, Ralf Steinmetz:
Reducing Authoring Costs of Online Training in Microelectronics Design by Reusing Design Documentation Content. MSE 2003: 57-58 - [c40]Alexandre Casacurta, Marcel Furtado Almeida, Ricardo Augusto da Luz Reis:
A Visual Simulation Tool at Layout Level. MSE 2003: 110-111 - [c39]Ricardo Augusto da Luz Reis:
Power and Timing Driven Physical Design Automation. PATMOS 2003: 348-357 - [c38]Renato Fernandes Hentschke, Ricardo Augusto da Luz Reis:
Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations. SBCCI 2003: 267- - [c37]Daniel Lima Ferrão, Gustavo Wilke, Ricardo Augusto da Luz Reis, José Luís Almada Güntzel:
Improving Critical Path Identification in Functional Timing Analysis. SBCCI 2003: 297-302 - [c36]Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis, José Luís Almada Güntzel:
A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. SBCCI 2003: 303- - [c35]Cristiano Lazzari, Cristiano Viana Domingues, José Luís Almada Güntzel, Ricardo Augusto da Luz Reis:
A New Macro-cell Generation Strategy for three metal layer CMOS Technologies. VLSI-SOC 2003: 193-197 - [c34]Cristiano Lazzari, Cristiano Viana Domingues, José Luís Güntzel, Ricardo Reis:
A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits. VLSI-SoC (Selected Papers) 2003: 197-211 - [c33]Renato Fernandes Hentschke, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis:
A study on the performance of fast initial placement algorithms. VLSI-SOC 2003: 204- - [e3]Lillian N. Cassel, Ricardo Augusto da Luz Reis:
Informatics Curricula and Teaching Methods, IFIP TC3 / WG3.2 Conference on Informatics Curricula, Teaching Methods and Best Practics (ICTEM 2002), July 10-12, 2002, Florianópolis, SC, Brazil. IFIP Conference Proceedings 245, Kluwer 2003, ISBN 1-4020-7266-X [contents] - [e2]Manfred Glesner, Ricardo Augusto da Luz Reis, Hans Eveking, Vincent John Mooney III, Leandro Soares Indrusiak, Peter Zipf:
IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003. Technische Universität Darmstadt, Insitute of Microelectronic Systems 2003, ISBN 3-901882-17-0 [contents] - 2002
- [c32]Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis:
Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments. DATE 2002: 1130 - [c31]Lillian N. Cassel, Gordon Davies, Deepak Kumar, Ralf Denzer, A. E. N. Hacquebard, Richard J. LeBlanc, Luiz Ernesto Merkle, Fred Mulder, Zeljko Panian, Ricardo Augusto da Luz Reis, Eric Roberts, Paolo Rocchi, Maarten van Veen, Avelino F. Zorzo:
Computing: The Shape of an Evolving Discipline. Informatics Curricula and Teaching Methods 2002: 131-138 - [c30]Fernanda Gusmão de Lima Kastensmidt, Luigi Carro, Raoul Velazco, Ricardo Augusto da Luz Reis:
Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller. IOLTW 2002: 194 - [c29]Fernanda Lima, Luigi Carro, Raul Velazco, Ricardo Reis:
Injecting Multiple Upsets in a SEU tolerant 8051 Micro-controller. LATW 2002: 120-125 - [c28]José Luís Güntzel, Gustavo Wilke, Márcio Bystronski, Ana Cristina Medina Pinto, Ricardo Reis:
A Comparison Between Testability Measures Applied to Complex Gates. LATW 2002: 144-149 - [c27]Renato Fernandes Hentschke, Felipe S. Marques, Fernanda Lima, Luigi Carro, Altamiro Amadeu Susin, Ricardo Reis:
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy. SBCCI 2002: 95-100 - [c26]Sandro Sawicki, Lisane B. de Brisolara, Leandro S. lndrusiak, Ricardo Reis:
Collaborative Design Using a Shared Object Spaces Infrastructure. SBCCI 2002: 163-168 - [c25]Alex Panato, Marcelo Barcelos, Ricardo Reis:
An IP of an Advanced Encryption Standard for Altera" Devices. SBCCI 2002: 197-202 - [c24]Marcelo de Oliveira Johann, Glauco Borges Valim dos Santos, Ricardo Augusto da Luz Reis:
A LEGAL Algorithm Following Global Routing. SBCCI 2002: 271-276 - [c23]Gustavo Wilke, José Luís Güntzel, Márcio Bystronski, Ana Cristina Medina Pinto, Ricardo Reis:
Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing. SBCCI 2002: 277-282 - 2001
- [j4]Érika F. Cota, Fernanda Lima, Sana Rezgui, Luigi Carro, Raoul Velazco, Marcelo Lubaszewski, Ricardo Reis:
Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults. J. Electron. Test. 17(2): 149-161 (2001) - [j3]Leandro Soares Indrusiak, Ricardo Augusto da Luz Reis:
3D integrated circuit layout visualization using VRML. Future Gener. Comput. Syst. 17(5): 503-511 (2001) - [j2]José Luís Almada Güntzel, Ricardo Augusto da Luz Reis:
Análise de Timing Funcional de Circuitos VLSI Contendo Portas Complexas. RITA 8(1): 111-142 (2001) - [c22]Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis:
Distributed Collaborative Design over Cave2 Framework. VLSI-SOC 2001: 97-108 - [c21]José Luís Güntzel, Ana Cristina Medina Pinto, Ricardo Reis:
A Timed Calculus for ATG-Based Timing Analysis with Complex Gates. LATW 2001: 234-239 - [c20]João Baptista dos Santos Martins, Fernando Moraes, Ricardo Reis:
Interconnection Length Estimation at Logic-Level. SBCCI 2001: 98-102 - [c19]Luciano Copello Ost, Marcos Mainardi, Leandro Soares Indrusiak, Ricardo Reis:
Jale3D - Platform-independent IC/MEMS Layout Edition Tool. SBCCI 2001: 174-179 - [c18]Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis:
LEGAL: An Algorithm for Simultaneous Net Routing. SBCCI 2001: 180-185 - 2000
- [j1]João Leonardo Fragoso, Eduardo Costa Pereira, Juergen Rochol, Sergio Bampi, Ricardo Reis:
Specification and design of an Ethernet Interface soft IP. J. Braz. Comput. Soc. 6(3): 5-12 (2000) - [c17]Fernanda Gusmão de Lima, Marcelo Barcelos, Juergen Rochol, Sergio Bampi, Ricardo Reis:
A frame stream controller IP. ISCAS 2000: 721-724 - [c16]Fernanda Gusmão de Lima, Eduardo D'Avila, Mauricio Moraes, Marcelo Lubaszewski, Ricardo Reis:
A Self-Testing Mask Programmable Matrix Using Built-in Current Sensing. LATW 2000: 15-19 - [c15]Júlio Henrique Araújo Pereira Machado, Carlos Tadeu Q. de Morais, Paulo Blauth Menezes, Ricardo Reis:
Structuring Web course pages as Automata: revising concepts. RIAO 2000: 150-159 - [c14]José Luís Güntzel, Ana Cristina Medina Pinto, Eduardo D'Avila, Ricardo Reis:
ATG-Based Timing Analysis of Circuits Containing Complex Gates. SBCCI 2000: 21-28 - [c13]Leandro Soares Indrusiak, Ricardo Augusto da Luz Reis:
From a Hyperdocument-Centric to an Object-Oriented Approach for the Cave Project. SBCCI 2000: 125-132 - [c12]João Leonardo Fragoso, Fernando Moraes, Ricardo Reis:
WTROPIC: A WWW-Based Macro-Cell Generator. SBCCI 2000: 133-138 - [c11]Marcelo O. Johann, Ricardo Reis:
Net by Net Routing with a New Path Search Algorithm. SBCCI 2000: 144-149 - [c10]Luciano Agostini, Georg Stemmer, A. Prado, Roberto Pacheco, T. Campos, Sergio Bampi, Ricardo Reis:
SisECO: Design of an Echo-Canceling IC for Base Band Modems. SBCCI 2000: 216-221 - [c9]Fernanda Gusmão de Lima, Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Ricardo Reis, Raoul Velazco, Sana Rezgui:
Designing a Radiation Hardened 8051-Like Micro-Controller. SBCCI 2000: 255-262 - [c8]F. K. Ferreira, Fernando Moraes, Ricardo Reis:
LASCA-Interconnect Parasitic Extraction Tool for Deep-Submicron IC Design. SBCCI 2000: 327-332 - [c7]Marcelo O. Johann, Andrew E. Caldwell, Ricardo Augusto da Luz Reis, Andrew B. Kahng:
Admissibility Proofs for the LCS* Algorithm. IBERAMIA-SBIA 2000: 236-244 - [e1]L. Miguel Silveira, Srinivas Devadas, Ricardo Augusto da Luz Reis:
VLSI: Systems on a Chip, IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99), December 1-4, 1999, Lisbon, Portugal. IFIP Conference Proceedings 162, Kluwer 2000, ISBN 0-7923-7731-1 [contents]
1990 – 1999
- 1999
- [c6]Fernanda Lima, Marcelo O. Johann, José Luís Almada Güntzel, Eduardo D'Avila, Luigi Carro, Ricardo Augusto da Luz Reis:
Designing a Mask Programmable Matrix for Sequential Circuits. VLSI 1999: 439-446 - [c5]Ricardo Augusto da Luz Reis, Leandro Soares Indrusiak:
Microelectronics Education Using WWW. MSE 1999: 43-44 - [c4]Ricardo Augusto da Luz Reis, Leandro Soares Indrusiak:
VRML and Microelectronics Education. MSE 1999: 84-85 - 1998
- [c3]Ricardo Reis, Leandro Soares Indrusiak:
Microelectronics Education using WWW and CAD Tools. SBCCI 1998: 31-37 - [c2]Leandro Soares Indrusiak, Ricardo Reis:
A Case Study for a WWW based CAD Framework. SBCCI 1998: 116-120 - [c1]José Luís Güntzel, Ana Cristina Medina Pinto, Fernando Moraes, Ricardo Reis:
An Improved Path Enumeration Method Considering Different Fall and Rise Gate Delays. SBCCI 1998: 208-212
Coauthor Index
Calebe Micael de Oliveira Conceição
aka: Calebe Conceição
aka: Calebe Conceição
José Luís Güntzel
aka: José Luís Almada Güntzel
aka: José Luís Almada Güntzel
Marcelo O. Johann
aka: Marcelo de Oliveira Johann
aka: Marcelo de Oliveira Johann
Fernanda Lima Kastensmidt
aka: Fernanda Gusmão de Lima Kastensmidt
aka: Fernanda Gusmão de Lima
aka: Fernanda Lima 0001
aka: Fernanda Gusmão de Lima Kastensmidt
aka: Fernanda Gusmão de Lima
aka: Fernanda Lima 0001
[c290] [c271] [c267] [c250] [c233] [j38] [j34] [c211] [c209] [j27] [c187] [c185] [c178] [c173] [j25] [c165] [c152] [c147] [c145] [c140] [c139] [c133] [c132] [c131] [j18] [c115] [j17] [c104] [c103] [c82] [c81] [c74] [c68] [j10] [j9] [c63] [c59] [j8] [c54] [c53] [j5] [c47] [c43] [c30] [c29] [c27] [j4] [c17] [c16] [c9] [c6]
[c290] [j50] [c275] [c271] [c270] [c268] [c267] [j43] [c262] [c261] [c259] [c258] [c257] [c251] [c250] [c248] [c244] [c242] [c240] [c239] [c238] [c235] [c233] [c232] [c231] [j38] [j37] [j36] [c226] [c225] [c222] [c215] [j35] [j34] [c212] [c211] [c210] [c207] [c205] [j31] [c201] [c196] [j28] [c184] [j26] [c160] [c156] [c155] [c154] [c149] [c144] [c138] [c137] [j20] [c110] [c109] [c102] [c93] [c76] [c72]
Luciano Ost
aka: Luciano Copello Ost
aka: Luciano Copello Ost
Tiago Reimann
aka: Tiago J. Reimann
aka: Tiago J. Reimann
Fábio G. R. G. da Silva
aka: Fabio G. Rossato G. da Silva
aka: Fabio G. Rossato G. da Silva
Adriel Ziesemer
aka: Adriel Mota Ziesemer
aka: Adriel Mota Ziesemer
Alexandra L. Zimpeck
aka: Alexandra Lackmann Zimpeck
aka: Alexandra Lackmann Zimpeck
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