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2000 – 2009
- 2008
[c8]Kyomin Sohn, Young-Ho Suh, Young-Jae Son, Daesik Yim, Kang-Young Kim, Dae-Gi Bae, Ted Kang, Hoon Lim, Soon-Moon Jung, Hyun-Geun Byun, Young-Hyun Jun, Kinam Kim:
A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy. ISSCC 2008: 386-387- 2007
- [j8]Sangbeom Kang, Woo Yeong Cho, Beak-Hyung Cho, KwangJin Lee, Changsoo Lee, Hyung-Rok Oh, Byung-Gil Choi, Qi Wang, Hye-Jin Kim, Mu-Hui Park, Yu-Hwan Ro, Suyeon Kim, Choong-Duk Ha, Ki-Sung Kim, Young-Ran Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Gitae Jeong, Hong-Sik Jeong, Kinam Kim, YunSueng Shin:
A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation. IEEE J. Solid State Circuits 42(1): 210-218 (2007) - 2006
- [j7]Hyung-Rok Oh, Beak-Hyung Cho, Woo Yeong Cho, Sangbeom Kang, Byung-Gil Choi, Hye-Jin Kim, Ki-Sung Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Gitae Jeong, Hong-Sik Jeong, Kinam Kim:
Enhanced write performance of a 64-mb phase-change random access memory. IEEE J. Solid State Circuits 41(1): 122-126 (2006) - [j6]Kyomin Sohn, Hyun-Sun Mo, Young-Ho Suh, Hyun-Geun Byun, Hoi-Jun Yoo:
An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology. IEEE J. Solid State Circuits 41(4): 823-830 (2006) - [c7]Sangbeom Kang, WooYeong Cho, Beak-Hyung Cho, Kwangjin Lee, Changsoo Lee, Hyung-Rok Oh, Byung-Gil Choi, Qi Wang, Hye-Jin Kim, Mu-Hui Park, Yu-Hwan Ro, Suyeon Kim, Du-Eung Kim, Kang-Sik Cho, Choong-Duk Ha, Young-Ran Kim, Ki-Sung Kim, Choong-Ryeol Hwang, Choong-Keun Kwak, Hyun-Geun Byun, YunSueng Shin:
A 0.1µm 1.8V 256Mb 66MHz Synchronous Burst PRAM. ISSCC 2006: 487-496 - 2005
- [j5]Kwang-Jin Lee, Hyo-Chang Kim, Uk-Rae Cho, Hyun-Geun Byun, Suki Kim:
A Low Jitter ADPLL for Mobile Applications. IEICE Trans. Electron. 88-C(6): 1241-1247 (2005) - [j4]Tae-Hyoung Kim, Kwang-Jin Lee, Uk-Rae Cho, Hyun-Geun Byun:
A High Resolution, Wide Range Digital Impedance Controller. IEICE Trans. Electron. 88-C(8): 1723-1725 (2005) - [j3]Woo Yeong Cho, Beak-Hyung Cho, Byung-Gil Choi, Hyung-Rok Oh, Sangbeom Kang, Ki-Sung Kim, Kyung-Hee Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Youngnam Hwang, SuJin Ahn, Gwan-Hyeob Koh, Gitae Jeong, Hongsik Jeong, Kinam Kim:
A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM). IEEE J. Solid State Circuits 40(1): 293-300 (2005) - [c6]Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun:
Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application. CICC 2005: 533-536 - [c5]Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun:
A pseudo-differential CMOS receiver insensitive to input common mode level. ISCAS (1) 2005: 440-443 - [c4]Tae-Hyoung Kim, Uk-Rae Cho, Hyun-Geun Byun:
A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch. ISCAS (2) 2005: 1847-1850 - 2004
- [j2]Yong-Jin Yoon, Hyuck In Kwon, Jong Duk Lee, Byung Gook Park, Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun:
Synchronous mirror delay for multiphase locking. IEEE J. Solid State Circuits 39(1): 150-156 (2004) - [c3]Kwang-Jin Lee, Cheol Kim, Suki Kim, Uk-Rae Cho, Hyun-Geun Byun:
Modeling and Testing of Faults in TCAMs. AsiaSim 2004: 521-528 - 2003
- [j1]Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, Jong-Cheol Lee, Dae-Gi Bae, Nam-Seog Kim, Kang-Young Kim, Young-Jae Son, Jeong-Suk Yang, Kwon-Il Sohn, Sung-Tae Kim, In-Yeol Lee, Kwang-Jin Lee, Tae-Gyoung Kang, Su-Chul Kim, Kee-Sik Ahn, Hyun-Geun Byun:
A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. IEEE J. Solid State Circuits 38(11): 1943-1951 (2003) - [c2]Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun:
Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface. CICC 2003: 391-394 - [c1]Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun:
New dynamic logic-level converters for high performance application. ISCAS (5) 2003: 93-96
Coauthor Index
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