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2020 – today
- 2024
[j50]Jinn-Shyan Wang
, Yu-Hsuan Kuo:
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency. Integr. 97: 102207 (2024)- [j49]Jinn-Shyan Wang, Pei-Yuan Chou:
Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3157-3164 (2024) - [c71]Tay-Jyi Lin, Ze Li, Yun-Cheng Chen, Chien-Tung Liu, Tien-Fu Chen, Jinn-Shyan Wang:
A 40-nm 13.88-TOPS/W FC-DNN Engine for 16-bit Intelligent Audio Processing Featuring Weight-Sharing and Approximate Computing. HCS 2024: 1 - 2023
- [j48]Tay-Jyi Lin, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang:
A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. IEEE Trans. Circuits Syst. II Express Briefs 70(12): 4564-4568 (2023) - 2022
- [c70]Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang:
A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. ASP-DAC 2022: 7-8 - 2020
- [c69]Jinn-Shyan Wang, Cheng-Xin Xue, Chien-Tung Liu, Tay-Jyi Lin:
A 0.21V 40nm NAND-ROM for IoT Sensing Systems with Long Standby Periods. ISCAS 2020: 1-4 - [c68]Jinn-Shyan Wang, Chien-Tung Liu, Chao-Hsiang Wang:
Low-Active-Energy and Low-Standby-Power Sub-threshold ROM for IoT Edge Sensing Systems. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [j47]Pei-Yuan Chou, Jinn-Shyan Wang:
An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2508-2518 (2019) - 2018
- [j46]Yung-Chen Chien, Jinn-Shyan Wang:
A 0.2 V 32-Kb 10T SRAM With 41 nW Standby Power for IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(8): 2443-2454 (2018) - [c67]Chien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei, Jinn-Shyan Wang, Tay-Jyi Lin:
A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs. SoCC 2018: 1-6 - [c66]Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Jyi Lin, Jinn-Shyan Wang:
Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications. SoCC 2018: 250-253 - 2017
- [j45]Jinn-Shyan Wang, Shih-Nung Wei:
Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2893-2906 (2017) - [j44]Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3341-3354 (2017) - [c65]Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin, Jinn-Shyan Wang:
An all-n-type dynamic adder for ultra-low-leakage IoT devices. ASICON 2017: 68-71 - [c64]Yi-Hsuan Ting, Tay-Jyi Lin, Cheng-Chun Chang, Chih-Chien Hu, Chingwei Yeh, Jinn-Shyan Wang:
Approximate Distributed Arithmetic for Variable-Latency Table Lookup. NGCAS 2017: 137-140 - 2016
- [j43]Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. Integr. 54: 24-36 (2016) - [j42]Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. IEEE Trans. Circuits Syst. II Express Briefs 63-II(10): 969-973 (2016) - [c63]Shang-Yi Li, Pei-Yuan Chou, Jinn-Shyan Wang:
Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction. ASP-DAC 2016: 262-267 - [c62]Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen:
Variable-length VLIW encoding for code size reduction in embedded processors. SoCC 2016: 296-299 - [c61]Yi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang, Jinn-Shyan Wang:
Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation. SoCC 2016: 350-355 - 2015
- [j41]Jinn-Shyan Wang, Chun-Yuan Cheng, Pei-Yuan Chou, Tzu-Yi Yang:
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture. IEEE J. Solid State Circuits 50(11): 2635-2644 (2015) - [j40]Jinn-Shyan Wang, Chun-Yuan Cheng:
An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 395-404 (2015) - [j39]Jinn-Shyan Wang, Yung-Chen Chien, Fengzhi Liu, Pei-Yao Chang:
A Calibration-Free PVTD-Variation-Tolerant Sensing Scheme for Footless-8T SRAM Designs. IEEE Trans. Multi Scale Comput. Syst. 1(3): 159-167 (2015) - [c60]Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang:
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. ASICON 2015: 1-4 - 2014
- [c59]Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang:
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS. A-SSCC 2014: 361-364 - [c58]Chung-Hsun Huang, Wei-Jen Chen, Keng-Jui Chang, Yi-Hsuan Ting, Keng-Chang Hsu, Yu-Fu Pan, Chao-Chun Chen, Yuan-Hua Chu, Tay-Jyi Lin, Jinn-Shyan Wang:
Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET). Hot Chips Symposium 2014: 1 - 2013
- [j38]Yi-Mao Hsiao, Yuan-Sun Chu, Jeng-Farn Lee, Jinn-Shyan Wang:
A high-throughput and high-capacity IPv6 routing lookup system. Comput. Networks 57(3): 782-794 (2013) - [j37]Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang:
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 597-601 (2013) - [c57]Tzu-Yuan Kuo, Keng-Jui Chang, Jen-Hsiang Lee, Zong-Wu He, Jinn-Shyan Wang:
An energy-efficient truly all-digital temperature sensor for SoC applications. ACM Great Lakes Symposium on VLSI 2013: 67-70 - [c56]Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang:
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159 - [c55]Jian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang:
Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS. ISSCC 2013: 426-427 - [c54]Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Variation-aware and adaptive-latency accesses for reliable low voltage caches. VLSI-SoC 2013: 358-363 - 2012
- [j36]Jinn-Shyan Wang, Pei-Yao Chang, Chi-Chang Lin:
Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier. IEICE Trans. Electron. 95-C(1): 172-175 (2012) - [j35]Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh:
An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 nm CMOS Technology. J. Circuits Syst. Comput. 21(8) (2012) - [j34]Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Yen-Hsiang Yu:
A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 908-912 (2012) - [j33]Chieh-Jen Cheng, Chao-Ching Wang, Wei-Chun Ku, Tien-Fu Chen, Jinn-Shyan Wang:
A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 841-854 (2012) - [j32]Chingwei Yeh, Yuan-Chang Chen, Jinn-Shyan Wang:
Towards Process Variation-Aware Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1929-1937 (2012) - [c53]Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, Jenn-Shyan Sheu:
Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment. VLSIC 2012: 186-187 - 2011
- [j31]Jinn-Shyan Wang, Pei-Yao Chang, Tai-Shin Tang, Jia-Wei Chen, Jiun-In Guo:
Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 183-192 (2011) - [j30]Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh:
Design of High-Performance CMOS Level Converters Considering PVT Variations. IEICE Trans. Electron. 94-C(5): 913-916 (2011) - [j29]Jia-Wei Chen, Hsiu-Cheng Chang, Jinn-Shyan Wang, Jiun-In Guo:
A dynamic quality-adjustable H.264 intra coder. IEEE Trans. Consumer Electron. 57(3): 1203-1211 (2011) - [c52]Jinn-Shyan Wang, Tsung-Han Hsieh, Keng-Jui Chang, Chingwei Yeh:
Low power shift registers for megabits CMOS image sensors. ASICON 2011: 17-20 - [c51]Jinn-Shyan Wang, Yung-Chen Chien, Jia-Hong Lin, Chun-Yuan Cheng, Ying-Ting Ma, Chung-Hsun Huang:
ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. ASICON 2011: 47-50 - [c50]Chingwei Yeh, Yan-Nan Liu, Jinn-Shyan Wang, Pei-Yao Chang:
Variation-resilient voltage generation for SRAM weak cell testing. ASICON 2011: 248-251 - [c49]Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng:
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. ASP-DAC 2011: 73-74 - [c48]Jinn-Shyan Wang, Keng-Jui Chang, Shu-Yi Yang, Tsung-Han Hsieh, Chingwei Yeh:
RSCE-aware ultra-low-voltage 40-nm CMOS circuits. ISOCC 2011: 131-134 - 2010
- [j28]Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh:
Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays. IEICE Trans. Electron. 93-C(10): 1540-1543 (2010) - [j27]Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang:
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop. IEEE J. Solid State Circuits 45(5): 1036-1047 (2010) - [c47]Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang:
A 55nm 1GHz one-cycle-locking de-skewing circuit. ISCAS 2010: 1755-1758
2000 – 2009
- 2009
- [j26]Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen, Jinn-Shyan Wang:
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices. IEEE J. Solid State Circuits 44(5): 1571-1581 (2009) - [j25]Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chi-Lin Liu, Tien-Fu Chen, Jiun-In Guo, Jinn-Shyan Wang:
VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism. IEEE Trans. Circuits Syst. Video Technol. 19(11): 1633-1645 (2009) - [j24]Hsiu-Cheng Chang, Jia-Wei Chen, Bing-Tsung Wu, Ching-Lung Su, Jinn-Shyan Wang, Jiun-In Guo:
A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications. IEEE Trans. Circuits Syst. Video Technol. 19(12): 1739-1754 (2009) - [c46]Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang:
A dynamic quality-scalable H.264 video encoder chip. ASP-DAC 2009: 125-126 - [c45]Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang:
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. DAC 2009: 587-592 - [c44]Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo:
A Dynamic Quality-scalable H.264 Video Encoder. ISCAS 2009: 1932 - 2008
- [j23]Chao-Ching Wang, Jinn-Shyan Wang, Chingwei Yeh:
High-Speed and Low-Power Design Techniques for TCAM Macros. IEEE J. Solid State Circuits 43(2): 530-540 (2008) - [c43]Tzu-Yuan Kuo, Jinn-Shyan Wang:
A low-voltage latch-adder based tree multiplier. ISCAS 2008: 804-807 - [c42]Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen, Jinn-Shyan Wang:
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices. ISSCC 2008: 390-391 - 2007
- [j22]Chien-Chang Lin, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Yi-Huan Ou-Yang, Ming-Chih Tsai, Jiun-In Guo, Jinn-Shyan Wang:
A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications. IEEE J. Solid State Circuits 42(1): 170-182 (2007) - [c41]Hsiu-Cheng Chang, Jia-Wei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li, Chun-Hao Chang, Ze-Min Chen, Wei-Sen Yang, Chien-Chang Lin, Ching-Wen Chen, Jinn-Shyan Wang, Jiun-In Guo:
A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip. ISSCC 2007: 280-603 - [c40]Jinn-Shyan Wang, Jian-Shiun Chen, Yi-Ming Wang, Chingwei Yeh:
A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS. ISSCC 2007: 294-604 - [c39]Chun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo:
A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. SiPS 2007: 521-526 - 2006
- [j21]Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh:
An AND-type match-line scheme for high-performance energy-efficient content addressable memories. IEEE J. Solid State Circuits 41(5): 1108-1119 (2006) - [j20]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang:
A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264. IEEE Trans. Circuits Syst. Video Technol. 16(4): 472-483 (2006) - [c38]Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang:
An 830mW, 586kbps 1024-bit RSA chip design. DATE Designers' Forum 2006: 24-29 - [c37]Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang:
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. DATE Designers' Forum 2006: 239-243 - [c36]Jia-Wei Chen, Chien-Chang Lin, Jiun-In Guo, Jinn-Shyan Wang:
Low Complexity Architecture Design of H.264 Predictive Pixel Compensator for HDTV Application. ICASSP (3) 2006: 932-935 - [c35]Jia-Wei Chen, Chun-Hao Chang, Chien-Chang Lin, Yi-Huan Yang, Jiun-In Guo, Jinn-Shyan Wang:
A Condition-based Intra Prediction Algorithm for H.264/AVC. ICME 2006: 1077-1080 - [c34]Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo:
A performance-aware IP core design for multimode transform coding using scalable-DA algorithm. ISCAS 2006 - [c33]Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu:
Design of STR level converters for SoCs using the multi-island dual-VDD design technique. ISCAS 2006 - [c32]Jinn-Shyan Wang, Yi-Ming Wang, Chun-Yuan Cheng, Yu-Chia Liu:
An improved SAR controller for DLL applications. ISCAS 2006 - [c31]Jinn-Shyan Wang, Chao-Ching Wang, Chingwei Yeh:
TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines. ISSCC 2006: 577-586 - 2005
- [j19]Jinn-Shyan Wang, Hung-Yu Li, Chingwei Yeh, Tien-Fu Chen:
Design techniques for single-low-VDD CMOS systems. IEEE J. Solid State Circuits 40(5): 1157-1165 (2005) - [j18]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen:
An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. IEEE Trans. Circuits Syst. Video Technol. 15(5): 704-715 (2005) - [c30]Yi-Ming Wang, Chang-Fen Hu, Yi-Jen Chen, Jinn-Shyan Wang:
An all-digital pulsewidth control loop. ISCAS (2) 2005: 1258-1261 - [c29]Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh:
A low-power high-SFDR CMOS direct digital frequency synthesizer. ISCAS (2) 2005: 1670-1673 - [c28]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang:
An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. ISCAS (5) 2005: 4517-4520 - [c27]Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo:
An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. ISLPED 2005: 155-160 - 2004
- [j17]Chung-Hsun Huang, Jinn-Shyan Wang, Chingwei Yeh, Chih-Jen Fang:
The CMOS carry-forward adders. IEEE J. Solid State Circuits 39(2): 327-336 (2004) - [j16]Yi-Ming Wang, Jinn-Shyan Wang:
A low-power half-delay-line fast skew-compensation circuit. IEEE J. Solid State Circuits 39(6): 906-918 (2004) - [c26]Yi-Ming Wang, Jinn-Shyan Wang:
A reliable low-power fast skew-compensation circuit. ASP-DAC 2004: 547-548 - [c25]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh:
A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding. ICME 2004: 1683-1686 - [c24]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen:
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. ISCAS (2) 2004: 141-144 - [c23]Jinn-Shyan Wang, Shang-Jyh Shieh, Ching-Wei Yeh, Yuan-Hsun Yeh:
Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs. ISCAS (2) 2004: 401-404 - [c22]Yi-Ming Wang, Jinn-Shyan Wang:
An all-digital 50% duty-cycle corrector. ISCAS (2) 2004: 925-928 - [c21]Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang:
Low-power fixed-width array multipliers. ISLPED 2004: 307-312 - 2003
- [j15]Hung-Cheng Wu, Tien-Fu Chen, Hung-Yu Li, Jinn-Shyan Wang:
Energy Efficient Caching-on-Cache Architectures for Embedded Systems. J. Inf. Sci. Eng. 19(5): 809-825 (2003) - [j14]Chung-Hsun Huang, Jinn-Shyan Wang:
High-performance and power-efficient CMOS comparators. IEEE J. Solid State Circuits 38(2): 254-262 (2003) - [j13]Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen:
Design theory and implementation for low-power segmented bus systems. ACM Trans. Design Autom. Electr. Syst. 8(1): 38-54 (2003) - 2002
- [j12]Yuan-Pao Hsu, Kao-Shing Hwang, Jinn-Shyan Wang:
An Associative Architecture of CMAC for Mobile Robot Motion Control. J. Inf. Sci. Eng. 18(2): 145-161 (2002) - [j11]Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang:
Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques. IEEE J. Solid State Circuits 37(1): 63-76 (2002) - [j10]Po-Hui Yang, Jinn-Shyan Wang:
Low-voltage pulsewidth control loops for SOC applications. IEEE J. Solid State Circuits 37(10): 1348-1351 (2002) - 2001
- [j9]Jinn-Shyan Wang, Ching-Rong Chang, Chingwei Yeh:
Analysis and design of high-speed and low-power CMOS PLAs. IEEE J. Solid State Circuits 36(8): 1250-1262 (2001) - [j8]Ching-Rong Chang, Jinn-Shyan Wang, Cheng-Hui Yang:
Low-power and high-speed ROM modules for ASIC applications. IEEE J. Solid State Circuits 36(10): 1516-1523 (2001) - [j7]Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang:
Charge-sharing alleviation and detection for CMOS domino circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 266-280 (2001) - [c20]Shang-Jyh Shieh, Jinn-Shyan Wang, Yuan-Hsun Yeh:
A contention-alleviated static keeper for high-performance domino logic circuits. ICECS 2001: 707-710 - [c19]Shang-Jyh Shieh, Jinn-Shyan Wang:
Design of low-power domino circuits using multiple supply voltages. ICECS 2001: 711-714 - [c18]Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang:
A high-speed CMOS incrementer/decrementer. ISCAS (4) 2001: 88-91 - [c17]Sheng-Yeh Lai, Jinn-Shyan Wang:
A high-efficiency CMOS charge pump circuit. ISCAS (4) 2001: 406-409 - 2000
- [j6]Jinn-Shyan Wang, Wayne Tseng, Hung-Yu Li:
Low-power embedded SRAM with the current-mode write technique. IEEE J. Solid State Circuits 35(1): 119-124 (2000) - [j5]Jinn-Shyan Wang, Po-Hui Yang, Duo Sheng:
Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops. IEEE J. Solid State Circuits 35(4): 583-592 (2000) - [j4]Jinn-Shyan Wang, Chung-Hsun Huang:
High-speed and low-power CMOS priority encoders. IEEE J. Solid State Circuits 35(10): 1511-1514 (2000) - [c16]Jinn-Shyan Wang, Po-Hui Yang:
Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier. ASP-DAC 2000: 225-228 - [c15]Yuan-Bao Hsu, Kao-Shing Hwang, Chien-Yuan Pao, Jinn-Shyan Wang:
A new CMAC neural network architecture and its ASIC realization. ASP-DAC 2000: 481-484 - [c14]Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang:
Charge sharing fault analysis and testing for CMOS domino logic circuits. Asian Test Symposium 2000: 435-440 - [c13]Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone:
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. DFT 2000: 329-337 - [c12]Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang:
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. ICCAD 2000: 387-390 - [c11]Jinn-Shyan Wang, Pei-Lung Lin, Wern-Ho Sheen, Duo Sheng, Yu-Ming Huang:
A compact adaptive equalizer IC for HIPERLAN system. ISCAS 2000: 265-268 - [c10]Jinn-Shyan Wang, Chun-Shing Huang:
A high-speed single-phase-clocked CMOS priority encoder. ISCAS 2000: 537-540 - [c9]Po-Hui Yang, Jinn-Shyan Wang, Yi-Ming Wang:
A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops. ISCAS 2000: 665-668 - [c8]Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone:
Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits. LATW 2000: 59-64
1990 – 1999
- 1999
- [j3]J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen:
Segmented bus design for low-power systems. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 25-29 (1999) - [c7]Ching-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang:
Technnology Mapping for Low Power. ASP-DAC 1999: 145-148 - [c6]Ching-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang:
Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs. DAC 1999: 62-67 - [c5]Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone:
Charge Sharing Fault Detection for CMOS Domino Logic Circuits. DFT 1999: 77-85 - [c4]Ching-Rong Chang, Jinn-Shyan Wang:
A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM. ISCAS (1) 1999: 254-257 - [c3]Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang:
A cell selection strategy for low power applications. ISCAS (6) 1999: 416-419 - 1998
- [c2]Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng:
Low-power embedded SRAM macros with current-mode read/write operations. ISLPED 1998: 282-287 - 1995
- [c1]Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu:
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ISCAS 1995: 1572-1575 - 1993
- [j2]Chung-Yu Wu, Kuo-Hsing Cheng, Jinn-Shyan Wang:
Analysis and design of a new race-free four-phase CMOS logic. IEEE J. Solid State Circuits 28(1): 18-25 (1993)
1980 – 1989
- 1989
- [j1]Jinn-Shyan Wang, Chung-Yu Wu, Ming-Kai Tsai:
CMOS nonthreshold logic (NTL) and cascode nonthreshold logic (CNTL) for high-speed applications. IEEE J. Solid State Circuits 24(3): 779-786 (1989)
Coauthor Index
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