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2020 – today
- 2024
[j66]Ayumu Yamada, Zhiyuan Huang, Naoko Misawa, Chihiro Matsui, Ken Takeuchi:
Comprehensive Analysis of Read Fluctuations in ReRAM CiM by Using Fluctuation Pattern Classifier. IEICE Trans. Electron. 107(10): 416-425 (2024)- [j65]Yuya Ichikawa, Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi:
REM-CiM: Attentional RGB-Event Fusion Multi-Modal Analog CiM for Area/Energy-Efficient Edge Object Detection during Both Day and Night. IEICE Trans. Electron. 107(10): 426-435 (2024) - [j64]Fuyuki Kihara, Chihiro Matsui, Ken Takeuchi:
3D Parallel ReRAM Computation-in-Memory for Hyperdimensional Computing. IEICE Trans. Electron. 107(10): 436-439 (2024) - [j63]Ken Takeuchi
, Tetsuya Iizuka, Kazuko Nishimura, Jerald Yoo:
Guest Editorial: Introduction to the Special Section on the 2023 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 59(10): 3119-3122 (2024) - [j62]Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi:
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 468-479 (2024) - [c80]Naoko Misawa, Tao Wang, Chihiro Matsui, Ken Takeuchi:
Embedded Transformer Hetero-CiM: SRAM CiM for 4b Read/Write-MAC Self-attention and MLC ReRAM CiM for 6b Read-MAC Linear&FC Layers. IMW 2024: 1-4 - 2023
- [j61]Chihiro Matsui, Ken Takeuchi:
Heterogeneous Integration of Precise and Approximate Storage for Error-Tolerant Workloads. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 491-503 (2023) - [j60]Shinsei Yoshikiyo, Naoko Misawa, Kasidit Toprasertpong, Shinichi Takagi, Chihiro Matsui, Ken Takeuchi:
Write Variation & Reliability Error Compensation by Layer-Wise Tunable Retraining of Edge FeFET LM-GA CiM. IEICE Trans. Electron. 106(7): 352-364 (2023) - [c79]Ken Takeuchi:
Foreword. A-SSCC 2023: 1-2 - [c78]Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi:
LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-Memory. ICCAD 2023: 1-9 - [c77]Ken Takeuchi:
Analog Computation-in-Memory (CiM) for AI Applications. ICICDT 2023: xvi - [c76]Takuto Nishimura, Yuya Ichikawa, Akira Goda, Naoko Misawa, Chihiro Matsui, Ken Takeuchi:
Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance. IMW 2023: 1-4 - [c75]Ken Takeuchi:
Neuromorphic Computation-in-Memory System (Invited). IRPS 2023: 1-4 - [c74]Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi:
ReRAM CiM Fluctuation Pattern Classification by CNN Trained on Artificially Created Dataset. IRPS 2023: 1-6 - 2022
- [c73]Yuya Ichikawa, Akira Goda, Chihiro Matsui, Ken Takeuchi:
Non-volatile Memory Application to Quantum Error Correction with Non-uniformly Quantized CiM. IMW 2022: 1-4 - [c72]Shinsei Yoshikiyo, Naoko Misawa, Kasidit Toprasertpong, Shinichi Takagi, Chihiro Matsui, Ken Takeuchi:
Edge Retraining of FeFET LM-GA CiM for Write Variation & Reliability Error Compensation. IMW 2022: 1-4 - [c71]Shinsei Yoshikiyo, Naoko Misawa, Chihiro Matsui, Ken Takeuchi:
Edge Computation-in-Memory for In-situ Class-incremental Learning with Knowledge Distillation. ISCAS 2022: 2953-2957 - [c70]Naoko Misawa, Kenta Taoka, Chihiro Matsui, Ken Takeuchi:
Domain Specific ReRAM Computation-in-Memory Design Considering Bit Precision and Memory Errors for Simulated Annealing. ISCAS 2022: 3289-3293 - [c69]Chihiro Matsui, Eitaro Kobayashi, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi:
Versatile FeFET Voltage-sensing Analog CiM for Fast & Small-area Hyperdimensional Computing. ISCAS 2022: 3403-3407 - 2021
- [c68]Kenta Taoka, Naoko Misawa, Shunsuke Koshino, Chihiro Matsui, Ken Takeuchi:
Simulated Annealing Algorithm & ReRAM Device Co-optimization for Computation-in-Memory. IMW 2021: 1-4 - [c67]Mamoru Fukuchi, Shun Suzuki, Kyosuke Maeda, Chihiro Matsui, Ken Takeuchi:
BER Evaluation System Considering Device Characteristics of TLC and QLC NAND Flash Memories in Hybrid SSDs with Real Storage Workloads. ISCAS 2021: 1-4 - [c66]Daiki Kojima, Ken Takeuchi:
Error Suppression of Last-Programmed Word-Line for Real Usage of 3D-NAND Flash Memory. ISCAS 2021: 1-4 - [c65]Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag:
SE1: What Technologies Will Shape the Future of Computing? ISSCC 2021: 537-538 - [c64]Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi:
Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage Sensing. VLSI Circuits 2021: 1-2 - 2020
- [j59]Mamoru Fukuchi, Chihiro Matsui, Ken Takeuchi:
System Performance Comparison of 3D Charge-Trap TLC NAND Flash and 2D Floating-Gate MLC NAND Flash Based SSDs. IEICE Trans. Electron. 103-C(4): 161-170 (2020) - [j58]Yoshiki Takai, Mamoru Fukuchi, Chihiro Matsui, Reika Kinoshita, Ken Takeuchi:
Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs). IEICE Trans. Electron. 103-C(4): 171-180 (2020) - [j57]Ken Takeuchi, Brian P. Ginsburg:
Introduction to the Special Issue on the 2019 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 55(4): 843-845 (2020) - [j56]Shun Suzuki, Hiroki Aihara, Ken Takeuchi:
Privacy Protection NAND Flash System With Flexible Data-Lifetime Control by In-3-D Vertical Cell Processing. IEEE J. Solid State Circuits 55(10): 2802-2809 (2020) - [c63]Reika Kinoshita, Chihiro Matsui, Atsuya Suzuki, Shouhei Fukuyama, Ken Takeuchi:
Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance. ASP-DAC 2020: 319-324 - [c62]Yoshiki Kakuta, Reika Kinoshita, Hiroshi Kinoshita, Chihiro Matsui, Ken Takeuchi:
Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [j55]Chihiro Matsui, Ken Takeuchi:
Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage. Integr. 69: 62-74 (2019) - [j54]Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi:
Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories. IEEE J. Solid State Circuits 54(3): 745-754 (2019) - [j53]Ken Chang, Ken Takeuchi:
Introduction to the Special Issue on the 2018 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 54(4): 911-913 (2019) - [j52]Yoshiaki Deguchi, Toshiki Nakamura, Atsuna Hayakawa, Ken Takeuchi:
3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition. IEEE J. Solid State Circuits 54(6): 1800-1811 (2019) - [j51]Chihiro Matsui, Ken Takeuchi:
Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource Disaggregated Hybrid Storage With SCM and NAND Flash Memory. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1799-1810 (2019) - [c61]Toshiro Hiramoto, Katsumi Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Naoyuki Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Shinichi Nishizawa, Ichiro Omura, Hiromichi Ohashi, Kazuo Itou, Toshihiro Takakura, Munetoshi Fukui, Shinichi Suzuki, Ken Takeuchi, Masanori Tsukuda, Yohichiroh Numasawa:
Switching of 3300V Scaled IGBT by 5V Gate Drive. ASICON 2019: 1-3 - [c60]Chihiro Matsui, Ken Takeuchi:
Design of heterogeneously-integrated memory system with storage class memories and NAND flash memories. ASP-DAC 2019: 17-18 - [c59]Shun Suzuki, Kyoji Mizoguchi, Hikaru Watanabe, Toshiki Nakamura, Yoshiaki Deguchi, Keita Mizushina, Ken Takeuchi:
Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing. A-SSCC 2019: 231-234 - [c58]Koki Kamimura, Susumu Nohmi, Kenta Suzuki, Ken Takeuchi:
Parallel Product-Sum Operation Neuromorphic Systems with 4-bit Ferroelectric FET Synapses. ESSDERC 2019: 178-181 - [c57]Shouhei Fukuyama, Atsuna Hayakawa, Ryutaro Yasuhara, Shinpei Matsuda, Hiroshi Kinoshita, Ken Takeuchi:
Comprehensive Analysis of Data-Retention and Endurance Trade-Off of 40nm TaOx-based ReRAM. IRPS 2019: 1-6 - [c56]Kyoji Mizoguchi, Kyosuke Maeda, Ken Takeuchi:
Automatic Data Repair Overwrite Pulse for 3D-TLC NAND Flash Memories with 38x Data-Retention Lifetime Extension. IRPS 2019: 1-5 - [c55]Chihiro Matsui, Ken Takeuchi:
Self-Determining Resource Control in Multi-Tenant Data Center Storage with Future NV Memories. ISCAS 2019: 1-5 - 2018
- [j50]Yusuke Yamaga, Chihiro Matsui, Yukiya Sakaki, Ken Takeuchi:
Reliability Analysis of Scaled NAND Flash Memory Based SSDs with Real Workload Characteristics by Using Real Usage-Based Precise Reliability Test. IEICE Trans. Electron. 101-C(4): 243-252 (2018) - [j49]Hirofumi Takishita, Yutaka Adachi, Chihiro Matsui, Ken Takeuchi:
Analysis of SCM-Based SSD Performance in Consideration of SCM Access Unit Size, Write/Read Latencies and Application Request Size. IEICE Trans. Electron. 101-C(4): 253-262 (2018) - [j48]Yoshiaki Deguchi, Shun Suzuki, Ken Takeuchi:
Write and Read Frequency-Based Word-Line Batch VTH Modulation for 2-D and 3-D-TLC NAND Flash Memories. IEEE J. Solid State Circuits 53(10): 2917-2926 (2018) - [c54]Kota Tsurumi, Kenta Suzuki, Ken Takeuchi:
A 6.8 TOPS/W Energy Efficiency, 1.5µW Power Consumption, Pulse Width Modulation Neuromorphic Circuits for Near-Data Computing with SSD. A-SSCC 2018: 129-132 - [c53]Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi:
9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories. CICC 2018: 1-4 - [c52]Kazuki Maeda, Shinpei Matsuda, Ken Takeuchi, Ryutaro Yasuhara:
Observation and Analysis of Bit-by-Bit Cell Current Variation During Data-Retention of TaOx-based ReRAM. ESSDERC 2018: 46-49 - [c51]Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Ken Takeuchi:
Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x. ESSDERC 2018: 150-153 - [c50]Shouhei Fukuyama, Kazuki Maeda, Shinpei Matsuda, Ken Takeuchi, Ryutaro Yasuhara:
Suppression of endurance-stressed data-retention failures of 40nm TaOx-based ReRAM. IRPS 2018: 4-1 - [c49]Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi, Ken Takeuchi:
Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs. IRPS 2018: 7-1 - [c48]Mamoru Fukuchi, Yukiya Sakaki, Chihiro Matsui, Ken Takeuchi:
20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD. ISCAS 2018: 1-5 - [c47]Atsuna Hayakawa, Toshiki Nakamura, Yoshiaki Deguchi, Kazuki Maeda, Ken Takeuchi:
Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network. ISCAS 2018: 1-5 - [c46]Chihiro Matsui, Ken Takeuchi:
3ASCA: Application-Aware Autonomous SCM Capacity Adjustment for SCM and NAND Flash Pooled Storage. ISCAS 2018: 1-5 - [c45]Keita Mizushina, Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi:
Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition. ISCAS 2018: 1-5 - [c44]Shouhei Fukuyama, Shinpei Matsuda, Ryutaro Yasuhara, Ken Takeuchi:
Improvement of Endurance and Data-retention in 40nm TaOX-based ReRAM by Finalize Verify. NVMTS 2018: 1-4 - [c43]Reika Kinoshita, Chihiro Matsui, Shinpei Matsuda, Yutaka Adachi, Ken Takeuchi:
Maximizing Peformance/cost Figure of Merit of Storage-type SCM based SSD by Adding Small Capacity of Memory-type SCM. NVMTS 2018: 1-6 - [c42]Atsuya Suzuki, Chihiro Matsui, Ken Takeuchi:
Periodic Data Eviction Algorithm of SCM/NAND Flash Hybrid SSD with SCM Retention Time Constraint Capabilities at Extremely High Temperature. NVMTS 2018: 1-5 - [c41]Yutaka Adachi, Chihiro Matsui, Ken Takeuchi:
Double asymmetric-latency storage class memories (SCMs) for fast-write SCM, fast-read SCM & NAND flash hybrid SSDs. VLSI-DAT 2018: 1-4 - [c40]Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Iwai:
New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. VLSI Circuits 2018: 105-106 - 2017
- [j47]Tomoaki Yamada, Chihiro Matsui, Ken Takeuchi:
Workload-Based Co-Design of Non-Volatile Cache Algorithm and Storage Class Memory Specifications for Storage Class Memory/NAND Flash Hybrid SSDs. IEICE Trans. Electron. 100-C(4): 373-381 (2017) - [j46]Hirokazu Nosato, Hidenori Sakanashi, Eiichi Takahashi, Masahiro Murakawa, Hiroshi Aoki, Ken Takeuchi, Yasuo Suzuki:
Image Retrieval Method for Multiscale Objects from Optical Colonoscopy Images. Int. J. Biomed. Imaging 2017: 7089213:1-7089213:13 (2017) - [j45]Chihiro Matsui, Chao Sun, Ken Takeuchi:
Design of Hybrid SSDs With Storage Class Memory and NAND Flash Memory. Proc. IEEE 105(9): 1812-1821 (2017) - [j44]Chihiro Matsui, Asuka Arakawa, Chao Sun, Ken Takeuchi:
Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 510-519 (2017) - [c39]Hikaru Watanabe, Yoshiaki Deguchi, Ken Takeuchi:
MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage. A-SSCC 2017: 157-160 - [c38]Yoshiaki Deguchi, Ken Takeuchi:
Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data. A-SSCC 2017: 161-164 - [c37]Yoshiaki Deguchi, Toshiki Nakamura, Atsuro Kobayashi, Ken Takeuchi:
12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition. CICC 2017: 1-4 - [c36]Chihiro Matsui, Ken Takeuchi:
22% Higher performance, 2x SCM write endurance heterogeneous storage with dual storage class memory and NAND flash. ESSDERC 2017: 6-9 - [c35]Takashi Inose, Seiichi Aritome, Ryutaro Yasuhara, Satoshi Mishima, Ken Takeuchi:
Study of error repeatability and recovery in 40nm TaOx ReRAM. ESSDERC 2017: 10-13 - [c34]Kota Tsurumi, Masahiro Tanaka, Ken Takeuchi:
0.6 V operation, 16 % faster set/reset ReRAM boost converter with adaptive buffer voltage for ReRAM and NAND flash hybrid solid-state drives. ISQED 2017: 81-86 - 2016
- [j43]Hirofumi Takishita, Shuhei Tanakamaru, Sheyang Ning, Ken Takeuchi:
Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths. IEICE Trans. Electron. 99-C(4): 444-451 (2016) - [j42]Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi:
An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. IEEE J. Solid State Circuits 51(4): 1041-1050 (2016) - [j41]Sheyang Ning, Tomoko Ogura Iwasaki, Shuhei Tanakamaru, Darlene Viviani, Henry Huang, Monte Manning, Thomas Rueckes, Ken Takeuchi:
Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory. IEEE J. Solid State Circuits 51(8): 1938-1951 (2016) - [j40]Tomoya Ishii, Sheyang Ning, Masahiro Tanaka, Kota Tsurumi, Ken Takeuchi:
Adaptive Comparator Bias-Current Control of 0.6 V Input Boost Converter for ReRAM Program Voltages in Low Power Embedded Applications. IEEE J. Solid State Circuits 51(10): 2389-2397 (2016) - [j39]Chao Sun, Shun Okamoto, Shogo Hachiya, Tomoaki Yamada, Ken Takeuchi:
Design guidelines of storage class memory/flash hybrid solid-state drive considering system architecture, algorithm and workload characteristic. IEEE Trans. Consumer Electron. 62(3): 267-274 (2016) - [j38]Chao Sun, Ayumi Soga, Chihiro Matsui, Asuka Arakawa, Ken Takeuchi:
LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 115-128 (2016) - [j37]Shuhei Tanakamaru, Shogo Hosaka, Koh Johguchi, Hirofumi Takishita, Ken Takeuchi:
Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2208-2219 (2016) - [c33]Masahiro Tanaka, Kota Tsurumi, Tomoya Ishii, Ken Takeuchi:
Heterogeneously integrated program voltage generator for 1.0V operation NAND flash with best mix & match of standard CMOS process and NAND flash process. ESSCIRC 2016: 67-70 - [c32]Atsuro Kobayashi, Tsukasa Tokutomi, Ken Takeuchi:
Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centers. VLSI Circuits 2016: 1-2 - [p1]Chao Sun, Ken Takeuchi:
System-Level Considerations on Design of 3D NAND Flash Memories. 3D Flash Memories 2016: 349-375 - 2015
- [j36]Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi:
A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories. IEICE Trans. Electron. 98-C(1): 53-61 (2015) - [j35]Chao Sun, Asuka Arakawa, Ken Takeuchi:
SEA-SSD: A Storage Engine Assisted SSD With Application-Coupled Simulation Platform. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(1): 120-129 (2015) - [j34]Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi:
Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs). IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 771-780 (2015) - [j33]Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi:
Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 844-853 (2015) - [c31]Shogo Hachiya, Takahiro Onagi, Sheyang Ning, Ken Takeuchi:
Comprehensive comparison of 3D-TSV integrated solid-state drives (SSDs) with storage class memory and NAND flash memory. 3DIC 2015: TS6.2.1-TS6.2.5 - [c30]Tomoya Ishii, Shogo Hachiya, Sheyang Ning, Masahiro Tanaka, Ken Takeuchi:
0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications. A-SSCC 2015: 1-4 - [c29]Tsukasa Tokutomi, Masafumi Doi, Shogo Hachiya, Atsuro Kobayashi, Shuhei Tanakamaru, Ken Takeuchi:
7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage. ISSCC 2015: 1-3 - [c28]Senju Yamazaki, Shuhei Tanakamaru, Sakuya Suzuki, Tomoko Ogura Iwasaki, Shogo Hachiya, Ken Takeuchi:
Reliability enhancement of 1Xnm TLC for cold flash and millennium memories. VLSIC 2015: 112- - [c27]Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi:
Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory. VLSIC 2015: 128- - [c26]Shuhei Tanakamaru, Hiroki Yamazawa, Ken Takeuchi:
Privacy-protection solid-state storage (PP-SSS) system: Automatic lifetime management of internet-data's right to be forgotten. VLSIC 2015: 130- - 2014
- [j32]Koh Johguchi, Toru Egami, Kousuke Miyaji, Ken Takeuchi:
A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories. IEICE Trans. Electron. 97-C(4): 342-350 (2014) - [j31]Koh Johguchi, Kasuaki Yoshioka, Ken Takeuchi:
NAND Phase Change Memory with Block Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance. IEICE Trans. Electron. 97-C(4): 351-359 (2014) - [j30]Chao Sun, Kousuke Miyaji, Koh Johguchi, Ken Takeuchi:
A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(2): 382-392 (2014) - [j29]Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi:
NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 1119-1132 (2014) - [j28]Chao Sun, Tomoko Ogura Iwasaki, Takahiro Onagi, Koh Johguchi, Ken Takeuchi:
Cost, Capacity, and Performance Analyses for Hybrid SCM/NAND Flash SSD. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2360-2369 (2014) - [c25]Ken Takeuchi:
Hybrid solid-state storage system with storage class memory and NAND flash memory for big-data application. ISCAS 2014: 1046-1049 - [c24]Chao Sun, Ayumi Soga, Takahiro Onagi, Koh Johguchi, Ken Takeuchi:
A workload-aware-design of 3D-NAND flash memory for enterprise SSDs. ISQED 2014: 554-561 - [c23]Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi:
19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers. ISSCC 2014: 336-337 - [c22]Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi:
Application-aware solid-state drives (SSDs) with adaptive coding. VLSIC 2014: 1-2 - 2013
- [j27]Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi:
A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy. IEEE J. Solid State Circuits 48(9): 2239-2249 (2013) - [j26]Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi:
Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs). IEEE J. Solid State Circuits 48(11): 2920-2933 (2013) - [c21]Chao Sun, Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Ken Takeuchi:
Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression. ASP-DAC 2013: 81-82 - [c20]Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi:
Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme. ASP-DAC 2013: 83-84 - [c19]Ken Takeuchi:
Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memory. CICC 2013: 1-6 - [c18]Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi:
Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications. ISSCC 2013: 226-227 - 2012
- [j25]Ken Takeuchi, Teruyoshi Hatanaka, Shuhei Tanakamaru:
Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs). IEICE Electron. Express 9(8): 779-794 (2012) - [j24]Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi:
Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor. IEICE Trans. Electron. 95-C(4): 564-571 (2012) - [j23]Kousuke Miyaji, Ryoji Yajima, Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai, Ken Takeuchi:
Initialize and Weak-Program Erasing Scheme for High-Performance and High-Reliability Ferroelectric NAND Flash Solid-State Drive. IEICE Trans. Electron. 95-C(4): 609-616 (2012) - [j22]Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu:
Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 47(1): 3-7 (2012) - [j21]Shuhei Tanakamaru, Chinglin Hung, Ken Takeuchi:
Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming. IEEE J. Solid State Circuits 47(1): 85-96 (2012) - [j20]Teruyoshi Hatanaka, Ken Takeuchi:
NAND Controller System With Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD. IEEE J. Solid State Circuits 47(6): 1460-1468 (2012) - [j19]Kousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano, Ken Takeuchi:
Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1635-1643 (2012) - [c17]Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi:
A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy. ISSCC 2012: 232-234 - [c16]Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi:
Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme. ISSCC 2012: 424-426 - [c15]Ken Takeuchi, Jan Crols, Kevin Zhang, Mike Clinton, Tadaaki Yamauchi:
Robust VLSI circuit design & systems for sustainable society. ISSCC 2012: 500-501 - [c14]Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Chao Sun, Ken Takeuchi:
x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression. VLSIC 2012: 134-135 - 2011
- [j18]Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai, Ken Takeuchi:
Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell VTH Optimization of Ferroelectric (Fe)-NAND Flash Memories for Highly Reliable and Low Power Enterprise Solid-State Drives (SSDs). IEICE Trans. Electron. 94-C(4): 539-547 (2011) - [j17]Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD. IEEE J. Solid State Circuits 46(6): 1478-1487 (2011) - [j16]Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda, Shinji Miyano, Ken Takeuchi:
Improvement of Read Margin and Its Distribution by VTH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection. IEEE J. Solid State Circuits 46(9): 2180-2188 (2011) - [j15]Shuhei Tanakamaru, Ken Takeuchi:
A 0.5 V Operation V TH Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems. IEEE J. Solid State Circuits 46(10): 2406-2415 (2011) - [c13]Teruyoshi Hatanaka, Koh Johguchi, Ken Takeuchi:
A 3D-Integration method to compensate output voltage degradation of boost converter for compact Solid-State-Drives. 3DIC 2011: 1-4 - [c12]Kousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano, Ken Takeuchi:
Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM. CICC 2011: 1-4 - [c11]Ken Takeuchi:
Green high performance storage class memory & NAND flash memory hybrid SSD system. ISLPED 2011: 369-370 - [c10]Shuhei Tanakamaru, Chinglin Hung, Atsushi Esumi, Mitsuyoshi Ito, Kai Li, Ken Takeuchi:
95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm. ISSCC 2011: 204-206 - [c9]Ken Takeuchi, Ken Chang, Kevin Zhang, Tadaaki Yamauchi, Roberto Gastaldi:
Ultra-low voltage VLSIs for energy efficient systems. ISSCC 2011: 514-515 - 2010
- [j14]Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories. IEICE Trans. Electron. 93-C(3): 317-323 (2010) - [j13]Teruyoshi Hatanaka, Ryoji Yajima, Takeshi Horiuchi, Shouyu Wang, Xizhen Zhang, Mitsue Takahashi, Shigeki Sakai, Ken Takeuchi:
Ferroelectric (Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives. IEEE J. Solid State Circuits 45(10): 2156-2164 (2010) - [c8]Kentaro Honda, Kousuke Miyaji, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi:
Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor. CICC 2010: 1-4 - [c7]Pascal Urard, Ken Takeuchi, Kerry Bernstein, Hideto Hidaka, Michael Phan, Joo-Sun Choi, Bob Payne, Vladimir Stojanovic, Kees van Berkel, Takayasu Sakurai:
Silicon 3D-integration technology and systems. ISSCC 2010: 510-511
2000 – 2009
- 2009
- [j12]Ken Takeuchi:
Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD). IEEE J. Solid State Circuits 44(4): 1227-1234 (2009) - [c6]Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories. 3DIC 2009: 1-4 - [c5]Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories. ISLPED 2009: 87-92 - [c4]Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD. ISSCC 2009: 238-239 - [c3]Ken Takeuchi:
SSD memory subsystem innovation. ISSCC 2009: 504 - 2007
- [j11]Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima:
A 56-nm CMOS 99-mm2 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput. IEEE J. Solid State Circuits 42(1): 219-232 (2007) - 2006
- [c2]Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima:
A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput. ISSCC 2006: 507-516 - 2002
- [j10]Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Hiroshi Nakamura:
Circuit techniques for a 1.8-V-only NAND flash memory. IEEE J. Solid State Circuits 37(1): 84-89 (2002) - [j9]Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian J. Che:
A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed. IEEE J. Solid State Circuits 37(11): 1493-1501 (2002) - 2001
- [j8]Ken Takeuchi, Tomoharu Tanaka:
A dual-page programming scheme for high-speed multigigabit-scale NAND flash memories. IEEE J. Solid State Circuits 36(5): 744-751 (2001) - 2000
- [j7]Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, Koji Sakui:
A source-line programming scheme for low-voltage operation NAND flash memories. IEEE J. Solid State Circuits 35(5): 672-681 (2000)
1990 – 1999
- 1999
- [j6]Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui:
A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories. IEEE J. Solid State Circuits 34(5): 675-684 (1999) - [j5]Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui:
A 130-mm/2, 256-Mbit NAND flash with shallow trench isolation technology. IEEE J. Solid State Circuits 34(11): 1536-1543 (1999) - 1998
- [j4]Ken Takeuchi, Tomoharu Tanaka, Toru Tanzawa:
A multipage cell architecture for high-speed programming multilevel NAND flash memories. IEEE J. Solid State Circuits 33(8): 1228-1238 (1998) - 1997
- [j3]Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi:
A compact on-chip ECC for low cost flash memories. IEEE J. Solid State Circuits 32(5): 662-669 (1997) - 1996
- [j2]Ken Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura:
A double-level-Vth select gate array architecture for multilevel NAND flash memories. IEEE J. Solid State Circuits 31(4): 602-609 (1996)
1980 – 1989
- 1983
- [j1]Kazuyuki Hara, Tatsuo Gotoh, Tsuyoshi Miyazaki, Ken Takeuchi, Shigeru Mabuchi:
Relational Data Base Systems INQ and RIOS. IEEE Database Eng. Bull. 6(1): 22-28 (1983) - [c1]Akira Sekino, Ken Takeuchi, Takenori Makino, Katsuya Hakozaki, Tsugunori Doi, Tatsuo Goto:
Design Considerations for an Information Query Computer. Advanced Database Machine Architecture 1983: 130-167
Coauthor Index
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