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2020 – today
- 2024
[c91]Sun-Yang Tay, Victor Adrian, Rouli Fang, Yanshan Xie, Joseph S. Chang:
A 134-μW 50-MHz Quasi-Dynamic Comparator with A Novel Clock-Free Regenerative Latch. CICC 2024: 1-2- [c90]Rouli Fang, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Wei Shu, Sun-Yang Tay, Joseph Sylvester Chang:
A Novel Multi-Error-Lock-Trace (MELT) Test Structure for SET/SEU Characterization of Radiation-Hardened-By-Design Cells. MWSCAS 2024: 37-41 - 2023
- [c89]Jinhen Lee, Victor Adrian, Sun-Yang Tay, Yanshan Xie, Bah-Hwee Gwee, Joseph S. Chang:
A 3D-Printed Fourth-Order Stacked Filter for Integrated DC-DC Converters. ISCAS 2023: 1-5 - [c88]Yanshan Xie, Victor Adrian, Sun-Yang Tay, Jinhen Lee, Pak Kwong Chan, Joseph S. Chang:
An Accurate Digital Inductor Current Sensor for Current-Ripple-Based DC-DC Converters. ISCAS 2023: 1-5 - 2022
- [j45]Jun-Sheng Ng
, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee:
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1144-1157 (2022) - [c87]Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee:
Non-profiling based Correlation Optimization Deep Learning Analysis. ISCAS 2022: 2246-2250 - [c86]Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee:
An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations. ISCAS 2022: 2256-2260 - [c85]Jinhen Lee, Victor Adrian, Joseph S. Chang, Yin Sun, Sun-Yang Tay:
An Integrated DC-DC Converter with Novel Asymmetrical Segmented Power-Stages for Sustained High Power-Efficiencies. ISCAS 2022: 3053-3057 - [c84]Sun-Yang Tay, Victor Adrian, Joseph S. Chang, Jinhen Lee, Bah-Hwee Gwee:
A Versatile and Accurate Vector-Based Method for Modeling and Analyzing Planar Air-Core Inductors. ISCAS 2022: 3063-3067 - 2021
- [j44]Kwen-Siong Chong, Jun-Sheng Ng, Juncheng Chen, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Joseph Sylvester Chang, Bah-Hwee Gwee:
Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 343-356 (2021) - [c83]Yong Qu, Wei Shu, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang, Yue Li, Zixian Zheng, Joseph S. Chang:
A 12-W 96.1%-Efficiency eFuse-Based Ultrafast Battery Charger Supporting Wireless and USB Power Inputs. CICC 2021: 1-2 - [c82]Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee:
Normalized Differential Power Analysis - for Ghost Peaks Mitigation. ISCAS 2021: 1-5 - 2020
- [j43]Yong Qu, Wei Shu, Lei Qiu, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang, Joseph S. Chang:
A Low-Profile High-Efficiency Fast Battery Charger With Unifiable Constant-Current and Constant-Voltage Regulation. IEEE Trans. Circuits Syst. 67-I(11): 4099-4109 (2020) - [c81]Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Wei Shu, Joseph S. Chang:
Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller. ISCAS 2020: 1-5 - [c80]Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j42]Ravinder Dahiya, Deji Akinwande, Joseph S. Chang:
Flexible Electronic Skin: From Humanoids to Humans. Proc. IEEE 107(10): 2011-2015 (2019) - [j41]Joseph S. Chang, Tong Ge:
A Fully Additive Low-Temperature All-Air Low-Variation Printed/Flexible Electronics With Self-Compensation for Bending: Codesign From Materials, Design, Fabrication, and Applications. Proc. IEEE 107(10): 2106-2117 (2019) - [c79]Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang:
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. AsianHOST 2019: 1-7 - [c78]Yong Qu, Wei Shu, Joseph S. Chang:
A Monolithic I2V2-Controlled Dual-Phase LED Matrix Driver for Automotive Adaptive Driving Beam (ADB) Headlighting. CICC 2019: 1-4 - [c77]Yong Qu, Wei Shu, Yang Kang, Joseph S. Chang:
A 30V 2A Real-Time Programmable Solid-State Circuit Breaker with Improved Detection-Speed and Enhanced Power-Efficiency. ESSCIRC 2019: 157-160 - [c76]Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, W. Shu, Joseph S. Chang, Bah-Hwee Gwee:
Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. ISCAS 2019: 1-5 - 2018
- [j40]Jize Jiang, Wei Shu, Joseph S. Chang:
A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range. IEEE J. Solid State Circuits 53(8): 2331-2342 (2018) - [j39]Cui Keer, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang:
A Noise-Shaped Randomized Modulation for Switched-Mode DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 394-405 (2018) - [j38]Qing Liu, Wei Shu, Joseph S. Chang:
A 1-GS/s 11-Bit SAR-Assisted Pipeline ADC With 59-dB SNDR in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(9): 1164-1168 (2018) - [j37]Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang:
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 196-200 (2018) - [j36]F. N. U. Juanda, Wei Shu, Joseph S. Chang:
A Calibration-Free/DEM-Free 8-bit 2.4-GS/s Single-Core Digital-to-Analog Converter With a Distributed Biasing Scheme. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2299-2309 (2018) - [c75]Ne Kyaw Zwa Lwin, H. Sivaramakrishnan, Kwen-Siong Chong, Tong Lin, Wei Shu, Joseph S. Chang:
Single-Event-Transient Resilient Memory for DSP in Space Applications. DSP 2018: 1-5 - [c74]Wei Shu, Jize Jiang, Kwen-Siong Chong, Joseph Sylvester Chang:
Radiation Hardening By Design Integrated Circuits Enabling Low-Cost Satellites for Internet-of-Things. DSP 2018: 1-4 - [c73]Yin Sun, Victor Adrian, Tong Ge, Joseph S. Chang:
A Circuit for Reducing the Reverse Current in DCM DC-DC Converters. DSP 2018: 1-4 - [c72]Yong Qu, Wei Shu, Joseph S. Chang:
An Air-Core Coupled-Inductor Based Dual-Phase Output Stage for Point-of-Load Converters. ISCAS 2018: 1-4 - [c71]Yin Sun, Victor Adrian, Joseph S. Chang:
Power-Loss and Design Space Analyses for Fully-Integrated Switched-Mode DC-DC Converters. ISCAS 2018: 1-4 - [c70]Tong Ge, Zhou Jia, Joseph S. Chang:
Flexible Hybrid Electronics: Review and Challenges. ISCAS 2018: 1-5 - 2017
- [j35]Joseph S. Chang, Antonio F. Facchetti, Robert Reuss:
Guest Editorial Organic/Printed Electronics: A Circuits and Systems Perspective. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(1): 1-6 (2017) - [j34]Joseph S. Chang, Antonio F. Facchetti, Robert Reuss:
A Circuits and Systems Perspective of Organic/Printed Electronics: Review, Challenges, and Contemporary and Emerging Design Approaches. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(1): 7-26 (2017) - [j33]Jize Jiang, Wei Shu, Joseph S. Chang:
A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point. IEEE J. Solid State Circuits 52(3): 623-633 (2017) - [j32]F. N. U. Juanda, Wei Shu, Joseph S. Chang:
A 10-GS/s 4-Bit Single-Core Digital-to-Analog Converter for Cognitive Ultrawidebands. IEEE Trans. Circuits Syst. II Express Briefs 64-II(1): 16-20 (2017) - [j31]Jia Zhou, Tong Ge, Joseph S. Chang:
Printed Electronics: Effects of Bending and a Self-Compensation Means. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(3): 505-515 (2017) - [j30]Kwen-Siong Chong, Weng-Geng Ho, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang:
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 402-415 (2017) - [j29]Qing Liu, Wei Shu, Joseph S. Chang:
A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3444-3454 (2017) - [c69]Tong Ge, Jia Zhou, Yang Kang, Joseph S. Chang:
Review: A fully-additive printed electronics process with very-low process variations (Bent and unbent substrates) and PDK. ISCAS 2017: 1-4 - [c68]Qianqian Liu, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang:
A class-E RF power amplifier with a novel matching network for high-efficiency dynamic load modulation. ISCAS 2017: 1-4 - [c67]Yin Sun, Victor Adrian, Joseph S. Chang:
A novel high-rate hybrid window ADC design for monolithic digitally-controlled DC-DC converters. ISCAS 2017: 1-4 - [c66]Cui Keer, Victor Adrian, Yin Sun, Bah-Hwee Gwee, Joseph S. Chang:
A low-harmonics low-noise randomized modulation scheme for multi-phase DC-DC converters. NEWCAS 2017: 165-168 - 2016
- [c65]Nan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications. DATE 2016: 850-853 - [c64]Jize Jiang, Wei Shu, Kwen-Siong Chong, Tong Lin, Ne Kyaw Zwa Lwin, Joseph Sylvester Chang, Jingyuan Liu:
Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process. ISCAS 2016: 5-8 - [c63]Tong Ge, Huiqiao He, Jia Zhou, Yang Kang, Joseph S. Chang:
An investigation of THD of a BTL Class D amplifier. ISCAS 2016: 470-473 - [c62]Jia Zhou, Tong Ge, Joseph S. Chang:
Fully-additive printed electronics: Process Development Kit. ISCAS 2016: 862-865 - [c61]Tong Lin, Kwen-Siong Chong, Wei Shu, Ne Kyaw Zwa Lwin, Jize Jiang, Joseph S. Chang:
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process. ISCAS 2016: 966-969 - [c60]Weng-Geng Ho, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. ISCAS 2016: 1762-1765 - [c59]Huiqiao He, Tong Ge, Joseph Sylvester Chang:
A review on supply modulators for Envelope-Tracking Power Amplifiers. ISIC 2016: 1-4 - [c58]Yang Kang, Tong Ge, Huiqiao He, Joseph S. Chang:
A review of audio Class D amplifiers. ISIC 2016: 1-4 - [c57]Qianqian Liu, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang:
A high-efficiency Class-E polar power-amplifier with a novel digitally-controlled output matching network. ISIC 2016: 1-4 - [c56]Jia Yu, Tong Ge, Huiqiao He, Joseph S. Chang:
Substrate thickness effect on transformer. ISIC 2016: 1-4 - 2015
- [j28]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer. IET Circuits Devices Syst. 9(4): 309-318 (2015) - [j27]Linfei Guo, Tong Ge, Joseph S. Chang:
An Ultralow-Power Overcurrent Protection Circuit for Micropower Class D Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 62-II(10): 942-946 (2015) - [c55]Huiqiao He, Yang Kang, Jia Yu, Linfei Guo, Tong Ge, Joseph S. Chang:
A novel low-power high-efficiency 3-state filterless bang-bang class D amplifier. ICECS 2015: 93-96 - [c54]Jize Jiang, Wei Shu, Joseph Sylvester Chang, Jingyuan Liu:
A novel subthreshold voltage reference featuring 17ppm/°C TC within -40°C to 125°C and 75dB PSRR. ISCAS 2015: 501-504 - [c53]Yin Sun, Victor Adrian, Joseph S. Chang:
Design of a variable-delay window ADC for switched-mode DC-DC converters. ISCAS 2015: 1642-1645 - [c52]Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang:
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). ISCAS 2015: 1913-1916 - [c51]Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang:
A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. ISCAS 2015: 2589-2592 - 2014
- [j26]Linfei Guo, Tong Ge, Joseph Sylvester Chang:
A 101 dB PSRR, 0.0027% THD + N and 94% Power-Efficiency Filterless Class D Amplifier. IEEE J. Solid State Circuits 49(11): 2608-2617 (2014) - [j25]Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 989-1002 (2014) - [c50]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips. APCCAS 2014: 5-8 - [c49]Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho:
Synthesis of asynchronous QDI circuits using synchronous coding specifications. ISCAS 2014: 153-156 - [c48]Victor Adrian, Cui Keer, Bah-Hwee Gwee, Joseph Sylvester Chang:
A Randomized Modulation scheme for filterless digital Class D audio amplifiers. ISCAS 2014: 774-777 - [c47]Victor Adrian, Yin Sun, Joseph Sylvester Chang:
Design of a 5 GS/s fully-digital digital-to-analog converter. ISCAS 2014: 1548-1551 - [c46]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Ne Kyaw Zwa Lwin:
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. ISIC 2014: 320-323 - [c45]Salma Nashit, Victor Adrian, Cui Keer, Quoc-An Mai, Bah-Hwee Gwee, Joseph S. Chang:
A self-oscillating class D audio amplifier with dual voltage and current feedback. ISIC 2014: 480-483 - [c44]Tian-Shun Ng, Yin Sun, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang:
Design of an output stage for high switching frequency DC-DC converters. ISIC 2014: 488-491 - [c43]Linfei Guo, Tong Ge, Yang Kang, Huiqiao He, Joseph Sylvester Chang:
Analysis and design of PWM-in-PWM-out Class D Amplifiers. MWSCAS 2014: 254-257 - [c42]Huiqiao He, Tong Ge, Linfei Guo, Joseph S. Chang:
An investigation into the effect of carrier generators on power supply noise in PWM Class D amplifiers. MWSCAS 2014: 266-269 - [c41]Joseph S. Chang, Kwen-Siong Chong, Wei Shu, Tong Lin, Jize Jiang, Ne Kyaw Zwa Lwin, Yang Kang:
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process. MWSCAS 2014: 821-824 - [c40]Tong Ge, Joseph S. Chang, Tong Lin, Lei Zhang, Lim Geok Soon:
Fully-Additive printed electronics on flexible substrates: A Fully-Additive RFID tag. MWSCAS 2014: 825-828 - 2013
- [j24]Kok-Leong Chang, Joseph S. Chang, Bah-Hwee Gwee, Kwen-Siong Chong:
Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects. IEEE J. Emerg. Sel. Topics Circuits Syst. 3(1): 23-34 (2013) - [j23]Tong Lin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee:
An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks. IEEE J. Solid State Circuits 48(2): 573-586 (2013) - [c39]Jaeyoung Kim, Kwen-Siong Chong, Joseph Sylvester Chang, Pinaki Mazumder:
A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS. ACM Great Lakes Symposium on VLSI 2013: 83-88 - [c38]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. ISCAS 2013: 353-356 - [c37]Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. ISCAS 2013: 3022-3025 - 2012
- [j22]Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Joseph S. Chang:
Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors. IEEE J. Solid State Circuits 47(3): 769-780 (2012) - [c36]Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang:
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. ISCAS 2012: 492-495 - [c35]Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
A comparative study on asynchronous Quasi-Delay-Insensitive templates. ISCAS 2012: 1819-1822 - [c34]Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. ISCAS 2012: 1835-1838 - [c33]Kwen-Siong Chong, Joseph S. Chang, Idongesit E. Ebong, Yalcin Yilmaz, Pinaki Mazumder:
Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques. ISED 2012: 116-119 - [c32]Joseph S. Chang, Tong Ge, Edgar Sánchez-Sinencio:
Challenges of printed electronics on flexible substrates. MWSCAS 2012: 582-585 - 2011
- [j21]Yiqiong Shi, Bah-Hwee Gwee, Joseph Sylvester Chang:
Asynchronous DSP for low-power energy-efficient embedded systems. Microprocess. Microsystems 35(3): 318-328 (2011) - [j20]Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang:
Modeling and Synthesis of Asynchronous Pipelines. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 682-695 (2011) - [c31]Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A low-power dual-rail inputs write method for bit-interleaved memory cells. ISCAS 2011: 325-328 - [c30]Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, Yin Sun, Kok-Leong Chang:
Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation. ISCAS 2011: 1936-1939 - 2010
- [j19]Tong Ge, Joseph S. Chang:
Filterless class D amplifiers: power-efficiency and power dissipation. IET Circuits Devices Syst. 4(1): 48-56 (2010) - [j18]Wei Shu, Joseph Sylvester Chang:
IMD of Closed-Loop Filterless Class D Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(2): 518-527 (2010) - [j17]Victor Adrian, Joseph S. Chang, Bah-Hwee Gwee:
A Randomized Wrapped-Around Pulse Position Modulation Scheme for DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(9): 2320-2333 (2010) - [c29]Linfei Guo, Tong Ge, Joseph Sylvester Chang:
A micropower comparator for high power-efficiency hearing aid class D amplifiers. ISCAS 2010: 1248-1251
2000 – 2009
- 2009
- [j16]Wei Shu, Joseph Sylvester Chang:
Power Supply Noise in Analog Audio Class D Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(1): 84-96 (2009) - [j15]Victor Adrian, Joseph S. Chang, Bah-Hwee Gwee:
A Low-Voltage Micropower Digital Class-D Amplifier Modulator for Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 337-349 (2009) - [j14]Bah-Hwee Gwee, Joseph S. Chang, Yiqiong Shi, Chien-Chung Chua, Kwen-Siong Chong:
A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(7): 1349-1359 (2009) - [j13]Tong Ge, Joseph S. Chang:
Bang-Bang Control Class D Amplifiers: Total Harmonic Distortion and Supply Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(10): 2353-2361 (2009) - [c28]Wenfeng Yu, Wei Shu, Joseph Sylvester Chang:
A Low THD Analog Class D Amplifier based on Self-oscillating Modulation with Complete Feedback Network. ISCAS 2009: 2729-2732 - [c27]Tong Lin, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic. ISCAS 2009: 3162-3165 - 2008
- [j12]Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang:
Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 985-998 (2008) - [j11]Tong Ge, Joseph Sylvester Chang:
Modeling and Technique to Improve PSRR and PS-IMD in Analog PWM Class-D Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 55-II(6): 512-516 (2008) - [j10]Wei Shu, Joseph Sylvester Chang:
THD of Closed-Loop Analog PWM Class-D Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1769-1777 (2008) - [j9]Tong Ge, Joseph S. Chang:
Bang-Bang Control Class-D Amplifiers: Power-Supply Noise. IEEE Trans. Circuits Syst. II Express Briefs 55-II(8): 723-727 (2008) - [c26]Tong Ge, Joseph Sylvester Chang, Wei Shu:
PSRR of bridge-tied load PWM Class D Amps. ISCAS 2008: 284-287 - 2007
- [j8]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Design of several asynchronous-logic macrocells for a low-voltage micropower cell library. IET Circuits Devices Syst. 1(2): 161-169 (2007) - [j7]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low energy 16-bit Booth leapfrog array multiplier using dynamic adders. IET Circuits Devices Syst. 1(2): 170-174 (2007) - [j6]Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang:
Fast and memory-efficient invariant computation of ordinary Petri nets. IET Comput. Digit. Tech. 1(5): 612-624 (2007) - [j5]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang:
Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors. IEEE J. Solid State Circuits 42(9): 2034-2045 (2007) - [c25]Tong Ge, Joseph Sylvester Chang, Wei Shu:
Power Supply Noise in Bang-Bang Control Class D Amplifier. ISCAS 2007: 701-704 - [c24]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A Low Energy FFT/IFFT Processor for Hearing Aids. ISCAS 2007: 1169-1172 - 2006
- [j4]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids. IEEE Trans. Circuits Syst. II Express Briefs 53-II(9): 853-857 (2006) - [c23]Chong-Fatt Law, Bah-Hwee Gwee, Joseph S. Chang:
Optimized Algorithm for Computing Invariants of Ordinary Petri Nets. ACIS-ICIS 2006: 23-28 - [c22]Wei Shu, Joseph Sylvester Chang, Tong Ge, Meng Tong Tan:
Fourier Series Analysis for Nonlinearities Due to the Power Supply Noise in Open-Loop Class D Amplifiers. APCCAS 2006: 720-723 - [c21]Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang:
An acoustic noise suppression system with reduced musical artifacts. ISCAS 2006 - [c20]Tong Ge, Joseph Sylvester Chang, Wei Shu:
Modeling and analysis of PSRR in analog PWM class D amplifiers. ISCAS 2006 - [c19]Wei Shu, Joseph Sylvester Chang, Tong Ge, Meng Tong Tan:
Fourier series analysis of the nonlinearities in analog closed-loop PWM class D amplifiers. ISCAS 2006 - 2005
- [j3]Bah-Hwee Gwee, Joseph Sylvester Chang, Victor Adrian:
A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(10): 2007-2022 (2005) - [j2]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A micropower low-voltage multiplier with reduced spurious switching. IEEE Trans. Very Large Scale Integr. Syst. 13(2): 255-265 (2005) - [c18]Tong Ge, Meng Tong Tan, Joseph Sylvester Chang:
Design and analysis of a micropower low-voltage bang-bang control class D amplifier. ISCAS (1) 2005: 224-227 - [c17]Jingbo Yang, Meng Tong Tan, Joseph Sylvester Chang:
Modeling external feedback path of an ITE digital hearing instrument for acoustic feedback cancellation. ISCAS (2) 2005: 1326-1329 - [c16]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low-voltage micropower multipliers with reduced spurious switching. ISCAS (4) 2005: 4078-4081 - [c15]Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang:
A combined interpolatorless interpolation and high accuracy sampling process for digital class D amplifiers. ISCAS (6) 2005: 5405-5408 - 2004
- [c14]Victor Adrian, Bah-Hwee Gwee, Joseph Sylvester Chang:
A novel combined first and second order Lagrange interpolation sampling process for a digital class D amplifier. ISCAS (3) 2004: 233-260 - [c13]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders. ISCAS (2) 2004: 437-440 - 2003
- [c12]Bah-Hwee Gwee, Joseph Sylvester Chang:
A Hybrid Genetic Hill-climbing Algorithm for Four-Coloring Map Problems. HIS 2003: 252-261 - [c11]Chien-Chung Chua, Bah-Hwee Gwee, Joseph Sylvester Chang:
A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter. ISCAS (5) 2003: 381-384 - [c10]Bah-Hwee Gwee, Joseph Sylvester Chang, Victor Adrian, H. Amir:
A novel sampling process and pulse generator for a low distortion digital pulse-width modulator for digital class D amplifiers. ISCAS (4) 2003: 504-507 - [c9]Khia-Ho Chang, Bah-Hwee Gwee, Joseph Sylvester Chang:
A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File. VLSI 2003: 166-172 - 2002
- [c8]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low-voltage micropower asynchronous multiplier for hearing instruments. ISCAS (1) 2002: 865-868 - [c7]Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
Low-voltage asynchronous adders for low power and high speed applications. ISCAS (1) 2002: 873-876 - 2001
- [c6]Joseph Sylvester Chang, Bah-Hwee Gwee, Yong Seng Lon, Meng Tong Tan:
A novel low-power low-voltage Class D amplifier with feedback for improving THD, power efficiency and gain linearity. ISCAS (1) 2001: 635-638 - [c5]Meng Tong Tan, Joseph Sylvester Chang, Yit Chow Tong:
A novel low-voltage low-power wave digital filter bank for an intelligent noise reduction digital hearing instrument. ISCAS (2) 2001: 681-684 - [c4]Huiyun Li, Bah-Hwee Gwee, Joseph Sylvester Chang:
A digital Class D amplifier design embodying a novel sampling process and pulse generator. ISCAS (4) 2001: 826-829 - 2000
- [c3]Meng Tong Tan, Hock-Chuan Chua, Bah-Hwee Gwee, Joseph S. Chang:
An investigation on the parameters affecting total harmonic distortion in class D amplifiers. ISCAS 2000: 193-196
1990 – 1999
- 1999
- [c2]Meng Tong Tan, Joseph S. Chang, Yit Chow Tong:
A process-independent threshold voltage inverter-comparator for pulse width modulation applications. ICECS 1999: 1201-1204 - [c1]Meng Tong Tan, Joseph Sylvester Chang, Yit Chow Tong:
A novel self-tuning pulse width modulator based on master-slave architecture for a Class D amplifier. ISCAS (2) 1999: 164-167 - 1998
- [j1]Boh Lim Sim, Yit Chow Tong, Joseph Sylvester Chang, Chin-Tuan Tan:
A parametric formulation of the generalized spectral subtraction method. IEEE Trans. Speech Audio Process. 6(4): 328-337 (1998)
Coauthor Index
[c89] [j45] [c87] [c86] [c84] [j44] [c82] [c80] [c79] [c76] [j39] [j37] [j30] [c68] [c66] [c65] [c60] [c57] [j28] [c52] [c51] [j25] [c50] [c49] [c48] [c46] [c45] [c44] [j24] [j23] [c38] [c37] [j22] [c36] [c35] [c34] [j21] [j20] [c31] [c30] [j17] [j15] [j14] [c27] [j12] [j8] [j7] [j6] [j5] [c24] [j4] [c23] [c21] [j3] [j2] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c4] [c3]
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