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1990 – 1999
- 1993
[j2]B. Naveen, K. S. Raghunathan:
An Automatic Netlist-to-Schematic Generator. IEEE Des. Test Comput. 10(1): 36-41 (1993)- [c6]Suhail Ahmed, T. V. Nagesh, Ramoji Rao, B. Naveen, P. K. Fangaria, K. S. Raghunathan:
FLOR: A Hierarchical Floorplanner Under Vinyas VCX System - System Overview. VLSI Design 1993: 73-79 - [c5]P. Marimuthu, K. S. Raghunathan:
BEST: Bond Editor and Test Vector Translator. VLSI Design 1993: 111 - 1992
- [c4]B. Naveen, A. Savargaonkar, K. S. Raghunathan:
N2S: An Automatic Netlist to Schematic generator. VLSI Design 1992: 263-267 - [c3]K. R. Rao, K. S. Raghunathan:
Constrained Via Minimisation In Greedy Channel Routing. VLSI Design 1992: 268-272
1980 – 1989
- 1983
- [c2]K. S. Raghunathan, J. A. Barchanski, Gregor von Bochmann:
Relationship between performance parameters for transport and network services. SIGCOMM 1983: 129-135 - 1982
- [j1]Gregor von Bochmann, Eduard Cerny, Michel Gagné, Claude Jard, Alain Léveillé, Clement Lacaille, Michel Maksud, K. S. Raghunathan, Behçet Sarikaya:
Experience with Formal Specifications Using an Extended State Transition Model. IEEE Trans. Commun. 30(12): 2506-2513 (1982) - [c1]Gregor von Bochmann, Eduard Cerny, Michel Gagné, Claude Jard, Alain Léveillé, Clement Lacaille, Michel Maksud, K. S. Raghunathan, Behçet Sarikaya:
Some Experience with the Use of Formal Specifications. PSTV 1982: 171-185
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