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2020 – today
- 2024
[j4]Hiroshi Iwata
, Kokoro Yamasaki, Ken-ichi Yamaguchi:
Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements. J. Electron. Test. 40(4): 497-508 (2024)
2010 – 2019
- 2017
- [j3]Hiroshi Iwata, Nanami Katayama, Ken-ichi Yamaguchi:
Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests. IEICE Trans. Inf. Syst. 100-D(6): 1182-1189 (2017) - 2010
- [j2]Takahiro Nomura, Hiroshi Iwata, Kohji Higuchi, Kazushi Nakano:
Broadband robust PWM power amplifier using approximate 2DOF digital control. Artif. Life Robotics 15(1): 83-88 (2010) - [j1]Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara:
A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification. IEICE Trans. Inf. Syst. 93-D(7): 1857-1865 (2010) - [c4]Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara:
Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. Asian Test Symposium 2010: 206-211 - [c3]Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara:
A synthesis method to propagate false path information from RTL to gate level. DDECS 2010: 197-200 - [c2]Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara:
Enabling False Path Identification from RTL for Reducing Design and Test Futileness. DELTA 2010: 20-25 - [c1]Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara:
Test pattern selection to optimize delay test quality with a limited size of test set. ETS 2010: 260
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