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2020 – today
- 2024
[c10]Miroslav Skrbek, Pavel Kubalík, Martin Kohlík, Jaroslav Borecký, Robert Hülle:
Quantized Neural Network with Linearly Approximated Functions on Zynq FPGA. MECO 2024: 1-4- 2023
- [c9]Miroslav Skrbek, Pavel Kubalík, Martin Kohlík, Jaroslav Borecký, Robert Hülle:
Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA. MECO 2023: 1-4 - 2020
- [c8]Jaroslav Borecký, Robert Hülle, Petr Fiser:
Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing. DSD 2020: 684-691
2010 – 2019
- 2017
- [j1]Jaroslav Borecký, Martin Kohlík, Hana Kubátová:
Parity driven reconfigurable duplex system. Microprocess. Microsystems 52: 251-260 (2017) - 2016
- [c7]Jaroslav Borecký, Martin Kohlík, Hana Kubátová:
Parity Waterfall method. DDECS 2016: 21-26 - [c6]Jaroslav Borecký, Martin Kohlík, Pavel Vit, Hana Kubátová:
Enhanced Duplication Method with TMR-Like Masking Abilities. DSD 2016: 690-693 - 2014
- [c5]Pavel Vit, Jaroslav Borecký, Martin Kohlík, Hana Kubátová:
Fault Tolerant Duplex System with High Availability for Practical Applications. DSD 2014: 320-325 - 2012
- [c4]Martin Kohlík, Jaroslav Borecký, Hana Kubátová:
Miscellaneous Types of Partial Duplication Modifications for Availability Improvements. DSD 2012: 79-83 - 2011
- [c3]Jaroslav Borecký, Martin Kohlík, Pavel Kubalík, Hana Kubátová:
Fault Models Usability Study for On-line Tested FPGA. DSD 2011: 287-290 - 2010
- [c2]Jaroslav Borecký, Martin Kohlík, Hana Kubátová, Pavel Kubalík:
Faults Coverage Improvement Based on Fault Simulation and Partial Duplication. DSD 2010: 380-386
2000 – 2009
- 2009
- [c1]Jaroslav Borecký, Pavel Kubalík, Hana Kubátová:
Reliable Railway Station System Based on Regular Structure Implemented in FPGA. DSD 2009: 348-354
Coauthor Index
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