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ORCIDZeshan Chishti
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2020 – today
- 2023
[j5]Christina Giannoula
, Kailong Huang, Jonathan Tang, Nectarios Koziris, Georgios I. Goumas, Zeshan Chishti, Nandita Vijaykumar:
DaeMon: Architectural Support for Efficient Data Movement in Fully Disaggregated Systems. Proc. ACM Meas. Anal. Comput. Syst. 7(1): 16:1-16:36 (2023)- [c27]Christina Giannoula, Kailong Huang, Jonathan Tang, Nectarios Koziris, Georgios I. Goumas, Zeshan Chishti, Nandita Vijaykumar:
Architectural Support for Efficient Data Movement in Fully Disaggregated Systems. SIGMETRICS (Abstracts) 2023: 5-6 - [i6]Christina Giannoula, Kailong Huang, Jonathan Tang, Nectarios Koziris, Georgios I. Goumas, Zeshan Chishti, Nandita Vijaykumar:
DaeMon: Architectural Support for Efficient Data Movement in Disaggregated Systems. CoRR abs/2301.00414 (2023) - [i5]Christina Giannoula, Kailong Huang, Jonathan Tang, Nectarios Koziris, Georgios I. Goumas, Zeshan Chishti, Nandita Vijaykumar:
Architectural Support for Efficient Data Movement in Disaggregated Systems. CoRR abs/2301.09674 (2023) - 2021
- [c26]Abanti Basak, Zheng Qu, Jilan Lin, Alaa R. Alameldeen, Zeshan Chishti, Yufei Ding, Yuan Xie:
Improving Streaming Graph Processing Performance using Input Knowledge. MICRO 2021: 1036-1050 - 2020
- [c25]Abanti Basak, Jilan Lin, Ryan Lorica, Xinfeng Xie, Zeshan Chishti, Alaa R. Alameldeen, Yuan Xie:
SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads. ISPASS 2020: 12-23
2010 – 2019
- 2019
- [c24]Vinson Young, Zeshan A. Chishti, Moinuddin K. Qureshi:
TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems. ICCD 2019: 341-349 - [c23]Zeshan Chishti, Berkin Akin:
Memory system characterization of deep learning workloads. MEMSYS 2019: 497-505 - [c22]Berkin Akin, Zeshan A. Chishti, Alaa R. Alameldeen:
ZCOMP: Reducing DNN Cross-Layer Memory Footprint Using Vector Extensions. MICRO 2019: 126-138 - [i4]Vinson Young, Zeshan Chishti, Moinuddin K. Qureshi:
TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems. CoRR abs/1907.02184 (2019) - 2018
- [c21]Elvira Teran, Zeshan Chishti, Zhe Wang, Chris Wilkerson, Daniel A. Jiménez:
Flexible associativity for DRAM caches. CF 2018: 88-96 - [i3]Kevin K. Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Reducing DRAM Refresh Overheads with Refresh-Access Parallelism. CoRR abs/1805.01289 (2018) - 2017
- [c20]Jagadish B. Kotra, Narges Shahidi, Zeshan A. Chishti, Mahmut T. Kandemir:
Hardware-Software Co-design to Mitigate DRAM Refresh Overheads: A Case for Refresh-Aware Process Scheduling. ASPLOS 2017: 723-736 - [i2]Kevin K. Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Improving DRAM Performance by Parallelizing Refreshes with Accesses. CoRR abs/1712.07754 (2017) - 2016
- [j4]Ishwar Bhati, Mu-Tien Chang, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob:
DRAM Refresh Mechanisms, Penalties, and Trade-Offs. IEEE Trans. Computers 65(1): 108-121 (2016) - [c19]Paul Tschirhart, Jim Stevens, Zeshan Chishti, Bruce L. Jacob:
The Case for Associative DRAM Caches. MEMSYS 2016: 211-219 - [c18]Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, Zeshan Chishti:
Path confidence based lookahead prefetching. MICRO 2016: 60:1-60:12 - [i1]Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses. CoRR abs/1601.06352 (2016) - 2015
- [c17]Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob:
Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions. ISCA 2015: 235-246 - [c16]Paul Tschirhart, Jim Stevens, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob:
Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance. MEMSYS 2015: 179-190 - [c15]Manjunath Shevgoor, Sahil Koladiya, Rajeev Balasubramonian, Chris Wilkerson, Seth H. Pugsley, Zeshan Chishti:
Efficiently prefetching complex address patterns. MICRO 2015: 141-152 - 2014
- [c14]Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Improving DRAM performance by parallelizing refreshes with accesses. HPCA 2014: 356-367 - [c13]Seth H. Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L. Scott, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, Rajeev Balasubramonian:
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers. HPCA 2014: 626-637 - [c12]Jaewoong Sim, Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Hyesoon Kim:
Transparent Hardware Management of Stacked DRAM as Part of Memory. MICRO 2014: 13-24 - 2013
- [c11]Moinuddin K. Qureshi, Zeshan Chishti:
Operating SECDED-based caches at ultra-low voltage with FLAIR. DSN 2013: 1-11 - [c10]Ishwar Bhati, Zeshan Chishti, Bruce L. Jacob:
Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling. ISLPED 2013: 205-210 - 2011
- [j3]Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Wei Wu, Shih-Lien Lu:
Adaptive Cache Design to Enable Reliable Low-Voltage Operation. IEEE Trans. Computers 60(1): 50-63 (2011) - [c9]Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu:
Energy-efficient cache design using variable-strength error-correcting codes. ISCA 2011: 461-472 - 2010
- [c8]Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu:
Reducing cache power with low-cost, multi-bit error-correcting codes. ISCA 2010: 83-93 - [c7]Ahmed M. Amin, Zeshan Chishti:
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency. ISLPED 2010: 383-388
2000 – 2009
- 2009
- [j2]Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu:
Trading Off Cache Capacity for Low-Voltage Operation. IEEE Micro 29(1): 96-103 (2009) - [c6]Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu:
Improving cache lifetime reliability at ultra-low voltages. MICRO 2009: 89-99 - 2008
- [j1]Zeshan Chishti, T. N. Vijaykumar:
Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies. IEEE Trans. Computers 57(1): 69-81 (2008) - [c5]Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu:
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. ISCA 2008: 203-214 - [c4]Eric Chun, Zeshan Chishti, T. N. Vijaykumar:
Shapeshifter: Dynamically changing pipeline width and speed to address process variations. MICRO 2008: 411-422 - 2005
- [c3]Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar:
Optimizing Replication, Communication, and Capacity Allocation in CMPs. ISCA 2005: 357-368 - 2004
- [c2]T. N. Vijaykumar, Zeshan Chishti:
Wire Delay is Not a Problem for SMT (In the Near Future). ISCA 2004: 40-51 - 2003
- [c1]Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar:
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. MICRO 2003: 55-66
Coauthor Index
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