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2010 – 2019
- 2019
[j20]Krzysztof Kuchcinski:
Constraint programming in embedded systems design: Considered helpful. Microprocess. Microsystems 69: 24-34 (2019)- 2016
- [c70]Mehmet Ali Arslan, Flavius Gruian
, Krzysztof Kuchcinski, Andreas Karlsson:
Code generation for a SIMD architecture with custom memory organisation. DASIP 2016: 90-97 - 2015
- [c69]Mehmet Ali Arslan, Flavius Gruian, Krzysztof Kuchcinski:
Application-set driven exploration for custom processor architectures. ASAP 2015: 70-71 - [c68]Mehmet Ali Arslan, Krzysztof Kuchcinski, Flavius Gruian, Yangxurui Liu:
Programming support for reconfigurable custom vector architectures. PMAM@PPoPP 2015: 49-57 - [i1]Mehmet Ali Arslan, Flavius Gruian, Krzysztof Kuchcinski:
A Comparative Study of Scheduling Techniques for Multimedia Applications on SIMD Pipelines. CoRR abs/1502.07447 (2015) - 2014
- [j19]Usman Mazhar Mirza, Flavius Gruian, Krzysztof Kuchcinski:
Mapping streaming applications on multiprocessors with time-division-multiplexed network-on-chip. Comput. Electr. Eng. 40(8): 276-291 (2014) - [j18]Mehmet Ali Arslan, Krzysztof Kuchcinski:
Instruction selection and scheduling for DSP kernels. Microprocess. Microsystems 38(8): 803-813 (2014) - [c67]Peter Nilsson, Pietro Andreani, Krzysztof Kuchcinski, Joachim Rodrigues, Henrik Sjöland, Markus Törmänen, Lars-Erik Wernersson, Viktor Öwall:
Lessons from ten years of the international master's program in System-on-Chip. EWME 2014: 187-192 - 2013
- [c66]Mehmet Ali Arslan, Krzysztof Kuchcinski:
Instruction Selection and Scheduling for DSP Kernels on Custom Architectures. DSD 2013: 821-828 - [c65]Usman Mazhar Mirza, Flavius Gruian, Krzysztof Kuchcinski:
Design space exploration for streaming applications on multiprocessors with guaranteed service NoC. NoCArc@MICRO 2013: 35-40 - 2012
- [j17]Erwan Raffin, Christophe Wolinski, François Charot, Emmanuel Casseau, Antoine Floch, Krzysztof Kuchcinski, Stéphane Chevobbe, Stéphane Guyetant:
Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture. Int. J. Embed. Real Time Commun. Syst. 3(1): 1-30 (2012) - [j16]Kevin J. M. Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot:
Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation. ACM Trans. Reconfigurable Technol. Syst. 5(2): 10:1-10:38 (2012) - [c64]Mehmet Ali Arslan, Jörn W. Janneck, Krzysztof Kuchcinski:
Partitioning and mapping dynamic dataflow programs. ACSCC 2012: 1452-1456 - 2011
- [c63]Carl Christian Rolf, Krzysztof Kuchcinski:
Distributed Constraint Programming with Agents. ICAIS 2011: 320-331 - [c62]Björn Regnell, Krzysztof Kuchcinski:
Exploring Software Product Management decision problems with constraint solving - opportunities for prioritization and release planning. IWSPM 2011: 47-56 - 2010
- [c61]Antoine Floch, Christophe Wolinski, Krzysztof Kuchcinski:
Combined scheduling and instruction selection for processors with reconfigurable cell fabric. ASAP 2010: 167-174 - [c60]Erwan Raffin, Christophe Wolinski, François Charot, Krzysztof Kuchcinski, Stéphane Guyetant, Stéphane Chevobbe, Emmanuel Casseau:
Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture. DASIP 2010: 168-175
2000 – 2009
- 2009
- [j15]Christophe Wolinski, Krzysztof Kuchcinski, Erwan Raffin:
Automatic design of application-specific reconfigurable processor extensions with UPaK synthesis kernel. ACM Trans. Design Autom. Electr. Syst. 15(1): 1:1-1:36 (2009) - [c59]Kevin J. M. Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot:
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system. ASAP 2009: 145-152 - [c58]Christophe Wolinski, Krzysztof Kuchcinski, Erwan Raffin, François Charot:
Architecture-Driven Synthesis of Reconfigurable Cells. DSD 2009: 531-538 - [c57]Christophe Wolinski, Krzysztof Kuchcinski, Kevin J. M. Martin, Erwan Raffin, François Charot:
How Constrains Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor Extensions. ERSA 2009: 29-42 - [c56]Ali R. Iranpour, Krzysztof Kuchcinski:
Design space exploration for optimal memory mapping of data and instructions in multimedia applications to Scratch-Pad Memories. ESTIMedia 2009: 89-95 - [c55]Carl Christian Rolf, Krzysztof Kuchcinski:
Parallel Consistency in Constraint Programming. PDPTA 2009: 638-644 - [c54]Kevin J. M. Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot:
Constraint-Driven Identification of Application Specific Instructions in the DURASE System. SAMOS 2009: 194-203 - 2008
- [c53]Carl Christian Rolf, Krzysztof Kuchcinski:
Load-balancing methods for parallel and distributed constraint solving. CLUSTER 2008: 304-309 - [c52]Christophe Wolinski, Krzysztof Kuchcinski:
Automatic Selection of Application-Specific Reconfigurable Processor Extensions. DATE 2008: 1214-1219 - [c51]Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig:
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. DSD 2008: 345-352 - [c50]Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig:
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. FCCM 2008: 306-309 - [c49]Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig:
Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. FPL 2008: 391-396 - [c48]Carl Christian Rolf, Krzysztof Kuchcinski:
State-copying and Recomputation in Parallel Constraint Programming with Global Constraints. PDP 2008: 311-317 - 2007
- [c47]Christophe Wolinski, Krzysztof Kuchcinski:
Identification of Application Specific Instructions Based on Sub-Graph Isomorphism Constraints. ASAP 2007: 328-333 - [c46]Ana Fuentes Martinez, Krzysztof Kuchcinski:
Graph Matching Constraints for Synthesis with Complex Components. DSD 2007: 288-295 - [c45]Christophe Wolinski, Krzysztof Kuchcinski:
Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable Hardware. ERSA 2007: 175-181 - [c44]Mats Petter Pettersson, Krzysztof Kuchcinski:
A New Necessary Condition for Shortest Path Routing. NET-COOP 2007: 195-204 - [c43]Mats Petter Pettersson, Radoslaw Szymanek, Krzysztof Kuchcinski:
A CP-LP approach to network management in OSPF routing. SAC 2007: 311-315 - 2006
- [c42]Ali R. Iranpour, Krzysztof Kuchcinski:
Performance Improvement for H.264 Video Encoding using ILP Embedded Processor. DSD 2006: 515-521 - [c41]Ali R. Iranpour, Krzysztof Kuchcinski:
Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors. SAMOS 2006: 309-320 - 2005
- [c40]Per Andersson, Krzysztof Kuchcinski:
Java to Hardware Compilation for non Data Flow Applications. DSD 2005: 330-337 - [c39]Christophe Wolinski, Krzysztof Kuchcinski:
A Constraints Programming Approach for Fabric Cell Synthesis. DSD 2005: 356-363 - [c38]Henrik Svensson, Viktor Öwall, Krzysztof Kuchcinski:
Implementation aspects of a novel speech packet loss concealment method. ISCAS (3) 2005: 2867-2870 - [c37]Flavius Gruian, Per Andersson, Krzysztof Kuchcinski, Martin Schoeberl:
Automatic generation of application-specific systems based on a micro-programmed Java core. SAC 2005: 879-884 - 2004
- [c36]Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuchcinski:
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures. DATE 2004: 318-323 - [c35]Ali R. Iranpour, Krzysztof Kuchcinski:
Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4. DSD 2004: 262-269 - [c34]Christophe Wolinski, Krzysztof Kuchcinski, Maya B. Gokhale:
A Constraints Programming Approach to Communication Scheduling on SoPC Architectures. DSD 2004: 308-315 - [c33]Per Andersson, Krzysztof Kuchcinski:
Distinguished Paper: Automatic Local Memory Architecture Generation for Data Reuse in Custom Data Paths. ERSA 2004: 137-144 - [c32]Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuchcinski:
Data assignment and access scheduling exploration for multi-layer memory architectures. ESTIMedia 2004: 61-66 - [c31]Christophe Wolinski, Krzysztof Kuchcinski, Maya B. Gokhale:
A constraints programming approach to communication scheduling on SoPC architectures. FPGA 2004: 252 - 2003
- [j14]Krzysztof Kuchcinski, Christophe Wolinski:
Global approach to assignment and scheduling of complex behaviors based on HCDG and constraint programming. J. Syst. Archit. 49(12-15): 489-503 (2003) - [j13]Krzysztof Kuchcinski:
Constraints-driven scheduling and resource assignment. ACM Trans. Design Autom. Electr. Syst. 8(3): 355-383 (2003) - [c30]Radoslaw Szymanek, Krzysztof Kuchcinski:
Partial task assignment of task graphs under heterogeneous resource constraints. DAC 2003: 244-249 - [c29]Flavius Gruian, Krzysztof Kuchcinski:
Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution time. ISLPED 2003: 465-468 - 2002
- [c28]Per Andersson, Krzysztof Kuchcinski, Klas Nordberg, Patrick Doherty:
Integrating a Computational Model and a Run Time System for Image Processing on a UAV. DSD 2002: 102-109 - 2001
- [j12]Krzysztof Kuchcinski:
Constraints-driven design space exploration for distributed embedded systems. J. Syst. Archit. 47(3-4): 241-261 (2001) - [c27]Flavius Gruian, Krzysztof Kuchcinski:
LEneS: task scheduling for low-energy systems using variable supply voltage processors. ASP-DAC 2001: 449-455 - [c26]Radoslaw Szymanek, Krzysztof Kuchcinski:
A constructive algorithm for memory-aware task assignment and scheduling. CODES 2001: 147-152 - [c25]Krzysztof Kuchcinski, Christophe Wolinski:
Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming. DSD 2001: 220-227 - 2000
- [c24]Patrik Dohrty, Gösta H. Granlund, Krzysztof Kuchcinski, Erik Sandewall, Klas Nordberg, Erik Skarman, Johan Wiklund:
The WITAS Unmanned Aerial Vehicle Project. ECAI 2000: 747-755 - [c23]Per Andersson, Krzysztof Kuchcinski:
Performance Oriented Partitioning for Time-Multiplexed FPGA's. EUROMICRO 2000: 1060-1066 - [c22]Radoslaw Szymanek, Krzysztof Kuchcinski:
Task Assignment and Scheduling under Memory Constraints. EUROMICRO 2000: 1084-1090 - [c21]Radoslaw Szymanek, Flavius Gruian, Krzysztof Kuchcinski:
Digital Systems Design Using Constraint Logic Programming. PACPL 2000: 149-166
1990 – 1999
- 1999
- [c20]Krzysztof Kuchcinski:
Integrated Resource Assignment and Scheduling of Task Graphs Using Finite Domain Constraints. DATE 1999: 772-773 - [c19]Krzysztof Kuchcinski:
Synthesis of Distributed Embedded Systems. EUROMICRO 1999: 1022-1028 - [c18]Radoslaw Szymanek, Krzysztof Kuchcinski:
Design Space Exploration in System Level Synthesis under Memory Constraints. EUROMICRO 1999: 1029- - [c17]Flavius Gruian, Krzysztof Kuchcinski:
Low-Energy Directed Architecture Selection and Task Scheduling for System-Level Design. EUROMICRO 1999: 1296-1302 - 1998
- [c16]Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop:
Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems. DATE 1998: 132-138 - [c15]Krzysztof Kuchcinski:
An Approach to High-Level Synthesis Using Constraint Logic Programming. EUROMICRO 1998: 10074-10082 - [c14]Flavius Gruian, Krzysztof Kuchcinski:
Operation Binding and Scheduling for Low Power Using Constraint Logic Programming. EUROMICRO 1998: 10083-10090 - [c13]Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop:
Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems. EUROMICRO 1998: 10168- - 1997
- [j11]Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alexa Doboli:
System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search. Des. Autom. Embed. Syst. 2(1): 5-32 (1997) - [j10]Krzysztof Kuchcinski:
Design of hardware and software systems. J. Syst. Archit. 42(9-10): 663-664 (1997) - [j9]Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli:
Post-synthesis back-annotation of timing information in behavioral VHDL. J. Syst. Archit. 42(9-10): 725-741 (1997) - [c12]Xinli Gu, Erik Larsson, Krzysztof Kuchcinski, Zebo Peng:
A controller testability analysis and enhancement technique. ED&TC 1997: 153-157 - [c11]Krzysztof Kuchcinski:
Embedded System Synthesis by Timing Constraints Solving. ISSS 1997: 50-57 - 1996
- [j8]Petru Eles, Krzysztof Kuchcinski, Zebo Peng:
Synthesis of systems specified as interacting VHDL processes. Integr. 21(1-2): 113-138 (1996) - [c10]Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli:
Hardware/software partitioning of VHDL system specifications. EURO-DAC 1996: 434-439 - [c9]Peter Grün, Petru Eles, Krzysztof Kuchcinski, Zebo Peng:
Automatic Parallelization of a Petri Net-Based Design Representation for High-Level Synthesis. EUROMICRO 1996: 185-192 - [c8]Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alex Doboli:
Hardware/Software Partitioning with Iterative Improvement Heuristics. ISSS 1996: 71-76 - 1995
- [c7]Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli:
Timing constraint specification and synthesis in behavioral VHDL. EURO-DAC 1995: 452-457 - [c6]Xinli Gu, Krzysztof Kuchcinski, Zebo Peng:
An Efficient and Economic Partitioning Approach for Testability. ITC 1995: 403-412 - 1994
- [j7]Zebo Peng, Krzysztof Kuchcinski:
Automated transformation of algorithms into register-transfer level implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2): 150-166 (1994) - [c5]Petru Eles, Marius Minea, Krzysztof Kuchcinski, Zebo Peng:
Synthesis of VHDL concurrent processes. EURO-DAC 1994: 540-545 - [c4]Xinli Gu, Krzysztof Kuchcinski, Zebo Peng:
Testability analysis and improvement from VHDL behavioral specifications. EURO-DAC 1994: 644-649 - 1993
- [j6]Krzysztof Kuchcinski:
System level modelling and analysis of complex digital systems. Microprocess. Microprogramming 37(1-5): 91-94 (1993) - [c3]Krzysztof Kuchcinski, Wlodzimierz Drabent, Jan Maluszynski:
Automatic Diagnosis of VLSI Digital Circuits Using Algorithmic Debugging. AADEBUG 1993: 350-367 - 1992
- [j5]Xinli Gu, Krzysztof Kuchcinski, Zebo Peng:
An approach to testability analysis and improvement for VLSI systems. Microprocess. Microprogramming 35(1-5): 485-492 (1992) - [c2]Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Marius Minea:
Compiling VHDL into a high-level synthesis design representation. EURO-DAC 1992: 604-609 - 1991
- [j4]Xinli Gu, Krzysztof Kuchcinski, Zebo Peng:
Testability measure with reconvergent fanout analysis and its applications. Microprocessing and Microprogramming 32(1-5): 835-842 (1991) - 1990
- [j3]Krzysztof Kuchcinski, Zebo Peng:
Testability analysis in a VLSI high-level synthesis system. Microprocessing and Microprogramming 28(1-5): 295-300 (1990)
1980 – 1989
- 1988
- [j2]Krzysztof Kuchcinski, Zebo Peng:
Parallelism extraction from sequential programs for VLSI applications. Microprocess. Microprogramming 23(1-5): 87-92 (1988) - [c1]Krzysztof Kuchcinski, Bogdan Wiszniewski:
Path analysis of distributed programs. ACM Conference on Computer Science 1988: 320-328 - 1987
- [j1]Krzysztof Kuchcinski, Zebo Peng:
Microprogramming implementation of timed Petri nets. Integr. 5(2): 133-144 (1987)
Coauthor Index
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