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ORCIDIuliana Bacivarov
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2010 – 2019
- 2016
[j8]Pier Stanislao Paolucci
, Andrea Biagioni, Luis Gabriel Murillo, Frédéric Rousseau, Lars Schor, Laura Tosoratto, Iuliana Bacivarov, Robert Lajos Bücs, Clément Deschamps, Ashraf El Antably, Roberto Ammendola, Nicolas Fournel, Ottorino Frezza, Rainer Leupers, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Elena Pastorelli, Devendra Rai, Davide Rossetti, Francesco Simula:
Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms. J. Syst. Archit. 69: 29-53 (2016)- 2014
- [c30]Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele:
AdaPNet: Adapting process networks in response to resource variations. CASES 2014: 22:1-22:10 - [c29]Shin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele:
Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs. DAC 2014: 31:1-31:6 - [c28]Shin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele:
Reliability-aware mapping optimization of multi-core systems with mixed-criticality. DATE 2014: 1-4 - [c27]Pratyush Kumar, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele:
COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors. DATE 2014: 1-4 - [c26]Lars Schor, Iuliana Bacivarov, Luis Gabriel Murillo, Pier Stanislao Paolucci, Frédéric Rousseau, Ashraf El Antably, Robert Buecs, Nicolas Fournel, Rainer Leupers, Devendra Rai, Lothar Thiele, Laura Tosoratto, Piero Vicini, Jan Weinstock:
EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems. ISPA 2014: 182-189 - [i2]Pier Stanislao Paolucci, Iuliana Bacivarov, Devendra Rai, Lars Schor, Lothar Thiele, Hoeseok Yang, Elena Pastorelli, Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Francesco Simula, Laura Tosoratto, Piero Vicini:
EURETILE D7.3 - Dynamic DAL benchmark coding, measurements on MPI version of DPSNN-STDP (distributed plastic spiking neural net) and improvements to other DAL codes. CoRR abs/1408.4587 (2014) - 2013
- [j7]Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele:
Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs. J. Electron. Test. 29(4): 521-535 (2013) - [j6]Hoeseok Yang, Iuliana Bacivarov, Devendra Rai, Jian-Jia Chen, Lothar Thiele:
Real-time worst-case temperature analysis with temperature-dependent parameters. Real Time Syst. 49(6): 730-762 (2013) - [j5]Lothar Thiele, Lars Schor, Iuliana Bacivarov, Hoeseok Yang:
Predictability for timing and temperature in multiprocessor system-on-chip platforms. ACM Trans. Embed. Comput. Syst. 12(1s): 48:1-48:25 (2013) - [c25]Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele:
Expandable process networks to efficiently specify and explore task, data, and pipeline parallelism. CASES 2013: 5:1-5:10 - [c24]Devendra Rai, Lars Schor, Nikolay Stoimenov, Iuliana Bacivarov, Lothar Thiele:
Designing Applications with Predictable Runtime Characteristics for the Baremetal Intel SCC. Euro-Par Workshops 2013: 779-789 - [c23]Lars Schor, Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele:
Reliable and Efficient Execution of Multiple Streaming Applications on Intel's SCC Processor. Euro-Par Workshops 2013: 790-800 - [p3]Iuliana Bacivarov, Wolfgang Haid, Kai Huang, Lothar Thiele:
Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip. Handbook of Signal Processing Systems 2013: 867-903 - [i1]Pier Stanislao Paolucci, Iuliana Bacivarov, Gert Goossens, Rainer Leupers, Frédéric Rousseau, Christoph Schumacher, Lothar Thiele, Piero Vicini:
EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment. CoRR abs/1305.1459 (2013) - 2012
- [j4]Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele:
Worst-case temperature analysis for different resource models. IET Circuits Devices Syst. 6(5): 297-307 (2012) - [j3]Kai Huang, Wolfgang Haid, Iuliana Bacivarov, Matthias Keller, Lothar Thiele:
Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications. ACM Trans. Embed. Comput. Syst. 11(1): 8:1-8:23 (2012) - [c22]Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele:
Power agnostic technique for efficient temperature estimation of multicore embedded systems. CASES 2012: 61-70 - [c21]Lars Schor, Iuliana Bacivarov, Devendra Rai, Hoeseok Yang, Shin-Haeng Kang, Lothar Thiele:
Scenario-based design flow for mapping streaming applications onto on-chip many-core systems. CASES 2012: 71-80 - [c20]Olivera Jovanovic, Peter Marwedel, Iuliana Bacivarov, Lothar Thiele:
MAMOT: Memory-Aware Mapping Optimization Tool for MPSoC. DSD 2012: 743-750 - [c19]Shin-Haeng Kang, Hoeseok Yang, Lars Schor, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele:
Multi-objective mapping optimization via problem decomposition for many-core systems. ESTIMedia 2012: 28-37 - [c18]Christian Fabre, Iuliana Bacivarov, Eth Zürich, Ananda Basu, Martino Ruggiero, David Atienza, Eric Flamand:
PRO3D: programming for future 3D manycore architectures. INA-OCMC@HiPEAC 2012: 47-50 - [c17]Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele:
Fast worst-case peak temperature evaluation for real-time applications on multi-core systems. LATW 2012: 1-6 - [c16]Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele:
Worst-Case Temperature Guarantees for Real-Time Applications on Multi-core Systems. IEEE Real-Time and Embedded Technology and Applications Symposium 2012: 87-96 - 2011
- [c15]Peter Marwedel, Jürgen Teich, Georgia Kouveli, Iuliana Bacivarov, Lothar Thiele, Soonhoi Ha, Chanhee Lee, Qiang Xu, Lin Huang:
Mapping of applications to MPSoCs. CODES+ISSS 2011: 109-118 - [c14]Lothar Thiele, Lars Schor, Hoeseok Yang, Iuliana Bacivarov:
Thermal-aware system analysis and software synthesis for embedded multi-processors. DAC 2011: 268-273 - [c13]Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Jian-Jia Chen, Lothar Thiele:
Worst-case temperature analysis for real-time systems. DATE 2011: 631-636 - [c12]Christian Fabre, Iuliana Bacivarov, Ananda Basu, Martino Ruggiero, David Atienza, Eric Flamand, Jean-Pierre Krimm, Julien Mottin, Lars Schor, Pratyush Kumar, Hoeseok Yang, Devesh B. Chokshi, Lothar Thiele, Saddek Bensalem, Marius Bozga, Luca Benini, Mohamed M. Sabry, Yusuf Leblebici, Giovanni De Micheli, Diego Melpignano:
PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status. FMCO 2011: 277-293 - [c11]Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele:
Thermal-Aware Task Assignment for Real-Time Applications on Multi-Core Systems. FMCO 2011: 294-313 - [c10]Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele:
Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study. PATMOS 2011: 288-297 - 2010
- [p2]Iuliana Bacivarov, Wolfgang Haid, Kai Huang, Lothar Thiele:
Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip. Handbook of Signal Processing Systems 2010: 1007-1040
2000 – 2009
- 2009
- [j2]Wolfgang Haid, Kai Huang, Iuliana Bacivarov, Lothar Thiele:
Multiprocessor SoC software design flows. IEEE Signal Process. Mag. 26(6): 64-71 (2009) - [c9]Wolfgang Haid, Lars Schor, Kai Huang, Iuliana Bacivarov, Lothar Thiele:
Efficient execution of Kahn process networks on multi-processor systems using protothreads and windowed FIFOs. ESTIMedia 2009: 35-44 - [c8]Wolfgang Haid, Matthias Keller, Kai Huang, Iuliana Bacivarov, Lothar Thiele:
Generation and calibration of compositional performance analysis models for multi-processor systems. ICSAMOS 2009: 92-99 - [c7]Kai Huang, Iuliana Bacivarov, Jun Liu, Wolfgang Haid:
A modular fast simulation framework for stream-oriented MPSoC. SIES 2009: 74-81 - 2008
- [c6]Kai Huang, Iuliana Bacivarov, Fabian Hugelshofer, Lothar Thiele:
Scalably distributed SystemC simulation for embedded applications. SIES 2008: 271-274 - 2007
- [c5]Lothar Thiele, Iuliana Bacivarov, Wolfgang Haid, Kai Huang:
Mapping Applications to Tiled Multiprocessor Embedded Systems. ACSD 2007: 29-40 - 2006
- [c4]Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya:
Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. DATE Designers' Forum 2006: 166-171 - 2005
- [j1]Iuliana Bacivarov, Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya:
ChronoSym: a new approach for fast and accurate SoC cosimulation. Int. J. Embed. Syst. 1(1/2): 103-111 (2005) - [c3]Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed Amine Jerraya:
Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration. ASP-DAC 2005: 969-972 - 2003
- [c2]Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya:
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. DATE 2003: 10550-10555 - [p1]Sungjoo Yoo, Gabriela Nicolescu, Iuliana Bacivarov, Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya:
Multi-Level Software Validation for NoC. Networks on Chip 2003: 261-279 - 2002
- [c1]Iuliana Bacivarov, Sungjoo Yoo, Ahmed Amine Jerraya:
Timed HW-SW cosimulation using native execution of OS and application SW. HLDVT 2002: 51-56
Coauthor Index
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