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ORCIDGuido Gronthoud
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2010 – 2019
- 2012
[j5]Xiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido Gronthoud:
ADC Multi-Site Test Based on a Pre-test with Digital Input Stimulus. J. Electron. Test. 28(4): 393-404 (2012)
2000 – 2009
- 2009
- [c19]Xiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido Gronthoud:
Algorithms for ADC Multi-site Test with Digital Input Stimulus. ETS 2009: 45-50 - 2008
- [c18]Vladimir A. Zivkovic, Frank van der Heyden, Guido Gronthoud, Frans G. M. de Jong:
Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design. ETS 2008: 27-32 - 2007
- [j4]Jing Wang, Duncan M. Hank Walker, Xiang Lu, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J. A. M. van de Wiel, Stefan Eichenberger:
Modeling Power Supply Noise in Delay Testing. IEEE Des. Test Comput. 24(3): 226-234 (2007) - [j3]Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud:
Extending gate-level diagnosis tools to CMOS intra-gate faults. IET Comput. Digit. Tech. 1(6): 685-693 (2007) - [c17]Jens Anders
, Shaji Krishnan, Guido Gronthoud:
Re-configuration of sub-blocks for effective application of time domain tests. DATE 2007: 707-712 - [c16]Bram Kruseman, Ananta K. Majhi, Guido Gronthoud:
On Performance Testing with Path Delay Patterns. VTS 2007: 29-34 - [i1]Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen:
Memory Testing Under Different Stress Conditions: An Industrial Evaluation. CoRR abs/0710.4693 (2007) - 2006
- [j2]Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud:
Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits. J. Electron. Test. 22(4-6): 399-409 (2006) - [c15]Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger:
Power Supply Noise in Delay Testing. ITC 2006: 1-10 - [c14]Xinyue Fan, Will R. Moore, Camelia Hora, Mario Konijnenburg, Guido Gronthoud:
A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis. VTS 2006: 266-271 - 2005
- [j1]José Pineda de Gyvez, Guido Gronthoud, Rashid Amine:
Multi-VDD Testing for Analog Circuits. J. Electron. Test. 21(3): 311-322 (2005) - [c13]Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen:
Memory Testing Under Different Stress Conditions: An Industrial Evaluation. DATE 2005: 438-443 - [c12]Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen:
Memory testing improvements through different stress conditions. ESSCIRC 2005: 299-302 - [c11]Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud:
Stuck-open fault diagnosis with stuck-at model. ETS 2005: 182-187 - [c10]Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud:
A novel stuck-at based method for transistor stuck-open fault diagnosis. ITC 2005: 9 - [c9]Estella Silva, José Pineda de Gyvez, Guido Gronthoud:
Functional vs. multi-VDD testing of RF circuits. ITC 2005: 9 - [c8]Mohamed Azimane, Ananta K. Majhi, Guido Gronthoud, Maurice Lousberg:
A New Algorithm for Dynamic Faults Detection in RAMs. VTS 2005: 177-182 - 2004
- [c7]Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger:
On Hazard-free Patterns for Fine-delay Fault Testing. ITC 2004: 213-222 - [c6]José Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller:
Power Supply Ramping for Quasi-static Testing of PLLs. ITC 2004: 980-987 - 2003
- [c5]Daniel Arumí-Delgado, Rosa Rodríguez-Montañés, José Pineda de Gyvez, Guido Gronthoud:
Process-variability aware delay fault testing of ΔVT and weak-open defects. ETW 2003: 85-90 - [c4]José Pineda de Gyvez, Guido Gronthoud, Rashid Amine:
VDD Ramp Testing for RF Circuits. ITC 2003: 651-658 - [c3]Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger:
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model. VTS 2003: 345-350 - 2001
- [c2]Liquan Fang, Guido Gronthoud, Hans G. Kerkhoff:
Reducing analogue fault-simulation time by using high-level modelling in dotss for an industrial design. ETW 2001: 61-67 - 2000
- [c1]Will R. Moore, Guido Gronthoud, Keith Baker, Maurice Lousberg:
Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything? ITC 2000: 95-104
Coauthor Index
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