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ORCIDTsukasa Yamauchi
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2000 – 2009
- 2001
[c7]Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara:
Arithmetic Operation Oriented Reconfigurable Chip: RHW. FPL 2001: 618-622- 2000
- [c6]Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara:
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. FCCM 2000: 281-282
1990 – 1999
- 1998
- [c5]Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Tetsuya Higuchi:
Evolvable Hardware Chip for High Precision Printer Image Compression. AAAI/IAAI 1998: 486-491 - [c4]Isamu Kajitani, Tsutomu Hoshino, Daisuke Nishikawa, Hiroshi Yokoi, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Masaya Iwata, Didier Keymeulen, Tetsuya Higuchi:
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI. ICES 1998: 1-12 - 1996
- [c3]Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara:
SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method. FCCM 1996: 148-156 - [c2]Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara:
SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method. Parcella 1996: 128-136 - 1991
- [c1]Tsukasa Yamauchi, Akio Ishizuka, Toshiyuki Nakata, Nobuyuki Nishiguchi, Nobuhiko Koike:
PROTON: A Parallel Detailed Router on an MIMD Parallel Machine. ICCAD 1991: 340-343
Coauthor Index
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