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ORCIDVijay Pitchumani
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2010 – 2019
- 2013
[c25]Moongon Jung, Taigon Song, Yang Wan, Young-Joon Lee, Debabrata Mohapatra, Hong Wang, Greg Taylor, Devang Jariwala, Vijay Pitchumani, Patrick Morrow, Clair Webb, Paul Fischer, Sung Kyu Lim
:
How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. CICC 2013: 1-4- 2010
- [c24]Nagaraj Ns, Juan C. Rey, Jamil Kawa, Robert C. Aitken, Christian Lütkemeyer, Vijay Pitchumani, Andrzej J. Strojwas, Steve Trimberger:
Who solves the variability problem? DAC 2010: 218-219
2000 – 2009
- 2007
- [j10]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 645-658 (2007) - 2006
- [j9]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2637-2646 (2006) - [j8]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani:
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11(2): 325-345 (2006) - [c23]Vijay Pitchumani:
A Hitchhiker's Guide to the DFM Universe. APCCAS 2006: 1103-1106 - [c22]Sani R. Nassif, Vijay Pitchumani, Norma Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic:
Variation-aware analysis: savior of the nanometer era? DAC 2006: 411-412 - [c21]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD 2006: 178-185 - 2005
- [c20]Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen:
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? ASP-DAC 2005 - [c19]Vijay Pitchumani:
Embedded tutorial I: design for manufacturability. ASP-DAC 2005 - [c18]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani:
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) 2005: 6230-6233
1990 – 1999
- 1999
- [j7]Mehmet Emin Dalkiliç, Vijay Pitchumani:
Multi-schedule design space exploration: an alternative synthesis framework. Integr. 27(2): 87-112 (1999) - 1995
- [c17]M. Kemal Unaltuna, Vijay Pitchumani:
ANSA: A New Neural Net Based Scheduling Algorithm for High Level Synthesis. ISCAS 1995: 385-388 - 1994
- [c16]Mehmet Emin Dalkiliç, Vijay Pitchumani:
Optimal Operation Scheduling Using Resource Lower Bound Estimations. EDAC-ETC-EUROASIC 1994: 319-324 - [c15]Mehmet Emin Dalkiliç, Vijay Pitchumani:
Distributed data-path synthesis on a network of workstations. Great Lakes Symposium on VLSI 1994: 180-183 - [c14]Mehmet Emin Dalkiliç, Vijay Pitchumani:
A Multi-Schedule Approach to High-Level Synthesis. ICCD 1994: 572-575 - [c13]M. Kemal Unaltuna, Vijay Pitchumani:
A Stochastic Reward & Punishment Neural Network Algorithm for Circuit Bipartitioning. ISCAS 1994: 181-184 - [c12]Neeta Ganguly, Vijay Pitchumani:
HSIM1 and HSIM2: Object Oriented Algorithms for VHDL Simulation. VLSI Design 1994: 175-178 - 1993
- [c11]M. Kemal Unaltuna, Mehmet Emin Dalkiliç, Vijay Pitchumani:
Solving the scheduling problem in high level synthesis using a normalized mean field neural network. ICNN 1993: 275-280 - [c10]M. Kemal Unaltuna, Vijay Pitchumani:
Quadrisectioning Based Placement with a Normalized Mean Field Neural Network. ISCAS 1993: 2047-2050 - 1992
- [j6]Vijay Pitchumani, Pankaj Mayor, Nimish Radia:
A VHDL Fault Diagnosis Tool Using Functional Fault Models. IEEE Des. Test Comput. 9(2): 33-41 (1992) - [j5]Vinod Narayanan, Vijay Pitchumani:
Fault simulation on massively parallel SIMD machines algorithms, implementations and results. J. Electron. Test. 3(1): 79-92 (1992) - 1991
- [c9]Vijay Pitchumani, Pankaj Mayor, Nimish Radia:
A System for Fault Diagnosis and Simulation of VHDL Descriptions. DAC 1991: 144-150 - [c8]Vijay Pitchumani, Pankaj Mayor, Nimish Radia:
Fault Diagnosis using Functional Fault Models for VHDL descriptions. ITC 1991: 327-337
1980 – 1989
- 1989
- [c7]Vinod Narayanan, Vijay Pitchumani:
A Massively Parallel Algorithm for Fault Simulation on the Connection Machine. DAC 1989: 734-737 - [c6]Shantanu Ganguly, Vijay Pitchumani:
Compaction of a Routed Channel on the Connection Machine. DAC 1989: 779-782 - [c5]J. Lawrence Carter, Barry K. Rosen, Gordon L. Smith, Vijay Pitchumani:
Restricted symbolic evaluation is fast and useful. ICCAD 1989: 38-41 - 1988
- [j4]Vijay Pitchumani, Satish S. Soman:
Functional Test Generation Based on Unate Function Theory. IEEE Trans. Computers 37(6): 756-760 (1988) - [c4]Vinod Narayanan, Vijay Pitchumani:
: A Parallel Algorithm for Fault Simulation on the Connection Machine. ITC 1988: 89-93 - 1987
- [j3]Vijay Pitchumani, Qisui Zhang:
A Mixed HVH-VHV Algorithm for Three-Layer Channel Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(4): 497-502 (1987) - 1985
- [j2]Vijay Pitchumani, Edward P. Stabler:
Verification of Register Transfer Level Parallel Control Sequences. IEEE Trans. Computers 34(8): 761-765 (1985) - [c3]Zerksis D. Umrigar, Vijay Pitchumani:
An Experiment in Programming with Full First-Order Logic. SLP 1985: 40-47 - 1983
- [j1]Vijay Pitchumani, Edward P. Stabler:
An Inductive Assertion Method for Register Transfer Level Design Verification. IEEE Trans. Computers 32(12): 1073-1080 (1983) - [c2]Zerksis D. Umrigar, Vijay Pitchumani:
Formal verification of a real-time hardware design. DAC 1983: 221-227 - 1982
- [c1]Vijay Pitchumani, Edward P. Stabler:
A formal method for computer design verification. DAC 1982: 809-814
Coauthor Index
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