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ORCIDWei Deng 0001
Person information
- affiliation: Tsinghua University, Institute of Microelectronics, Beijing, China
- affiliation (PhD 2013): Tokyo Institute of Technology, Department of Electrical and Electronic Engineering, Japan
- affiliation: Apple Inc., Cupertino, CA, USA
Other persons with the same name
- Wei Deng — disambiguation page
- Wei Deng 0002 — Purdue University, West Lafayette, IN, USA
- Wei Deng 0003
![[0000-0001-7487-8519]](https://dblp.org/img/orcid-mark.12x12.png "0000-0001-7487-8519")
— outhwest University of Finance & Economics, China
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2020 – today
- 2024
[j40]Ziyi Lin, Haikun Jia, Ruichang Ma, Wei Deng, Zhihua Wang, Baoyong Chi:
A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer. IEEE J. Solid State Circuits 59(1): 253-267 (2024)- [j39]Fuyuan Zhao, Wei Deng, Haikun Jia, Wenjing Ye, Ruichen Wan, Zhihua Wang, Baoyong Chi:
A Band-Shifting Millimeter-Wave T/R Front-End Using Inductance-Mutation Transformer Technique for Multiband Phased-Array Transceivers. IEEE J. Solid State Circuits 59(5): 1323-1336 (2024) - [j38]Hongzhuo Liu, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Zhihua Wang, Baoyong Chi:
A Multireference PLL: Theory and Implementation. IEEE J. Solid State Circuits 59(7): 1981-1994 (2024) - [j37]Qixiu Wu, Wei Deng, Yaqian Sun, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi:
An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique. IEEE J. Solid State Circuits 59(8): 2441-2454 (2024) - [j36]Pingda Guan, Ruichang Ma, Haikun Jia, Wei Deng, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Qiuyu Peng, Teerachot Siriburanon, Robert Bogdan Staszewski, Zhihua Wang, Baoyong Chi:
A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces. IEEE J. Solid State Circuits 59(10): 3123-3141 (2024) - [j35]Xiangrong Huang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
A Compact E-Band Load-Modulation Balanced Power Amplifier in 65-nm CMOS. IEEE J. Solid State Circuits 59(10): 3172-3182 (2024) - [j34]Xiangrong Huang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi, Ziqiang Wang:
28 GHz Compact LNAs With 1.9 dB Minimum NF Using Folded Three-Coil Transformer and Dual-Feedforward Techniques for Phased Array Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3573-3583 (2024) - [j33]Yaqian Sun, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi:
Correction to "A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor-Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer". IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2904 (2024) - [c72]Huanyu Ge, Haikun Jia, Wei Deng, Ruichang Ma, Baoyong Chi:
A 194.9dBc/Hz FoM and 6.8-to-11.6GHz Quad-Core Dual-Mode Class-F VCO Featuring Wideband Flicker Noise Suppression. CICC 2024: 1-2 - [c71]Hongzhuo Liu, Wei Deng, Haikun Jia, Baoyong Chi:
An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter. CICC 2024: 1-2 - [c70]Junlong Gong, Wei Deng, Fuyuan Zhao, Haikun Jia, Wenjing Ye, Ruichen Wan, Baoyong Chi:
A 24.3-to-44.8 GHz Reconfigurable Dual-Band T/R Front-End with An Implicit Switch-based Antenna Interface Supporting 600MSym/s 64QAM. ISCAS 2024: 1-5 - [c69]Huanyu Ge, Haikun Jia, Wei Deng, Ruichang Ma, Zhihua Wang, Baoyong Chi:
19.5 A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique. ISSCC 2024: 356-358 - [c68]Ruichen Wan, Wei Deng, Qixiu Wu, Haikun Jia, W. Rui, Angxiao Yan, Haowen Cai, Sanming Hu, Zhihua Wang, Baoyong Chi:
A 132-to-163 GHz 4TX/4RX Distributed MIMO FMCW Radar Transceiver with Real-Time Reference-Clock Synchronization Enabling Cooperative Coherent Multistatic Imaging System. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j32]Haikun Jia, Pingda Guan, Wei Deng, Zhihua Wang, Baoyong Chi:
A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS. IEEE J. Solid State Circuits 58(2): 371-385 (2023) - [j31]Wei Deng, Zipeng Chen, Haikun Jia, Pingda Guan, Taikun Ma, Angxiao Yan, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, Baoyong Chi:
A D-Band Joint Radar-Communication CMOS Transceiver. IEEE J. Solid State Circuits 58(2): 411-427 (2023) - [j30]Yaqian Sun, Wei Deng, Haikun Jia, Yejun He, Zhihua Wang, Baoyong Chi:
A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique. IEEE J. Solid State Circuits 58(10): 2861-2873 (2023) - [j29]Xiangrong Huang, Haikun Jia, Shengnan Dong, Wei Deng, Zhihua Wang, Baoyong Chi:
A 24-30-GHz Four-Element Phased Array Transceiver With Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter for 5G Communication. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1839-1851 (2023) - [c67]Pingda Guan, Haikun Jia, Wei Deng, Ruichang Ma, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Zhihua Wang, Baoyong Chi:
A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology. A-SSCC 2023: 1-3 - [c66]Xiangrong Huang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBO. A-SSCC 2023: 1-3 - [c65]Xiangrong Huang, Haikun Jia, Wei Deng, Chuanming Zhu, Zhihua Wang, Xuzhi Liu, Zhiming Chen, Baoyong Chi:
A 4-Element 4-Beam Ka-Band Phased-Array Receiver Using Mesh Topology in 65 nm CMOS. A-SSCC 2023: 1-3 - [c64]Dongze Li, Wei Deng, Xintao Li, Ruiheng Qiu, Haikun Jia, Xiangrong Huang, Ziyuan Guo, Baoyong Chi:
A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOS. A-SSCC 2023: 1-3 - [c63]Ziyi Lin, Haikun Jia, Chuanming Zhu, Wei Deng, Huabing Liao, Bao Shi, Lujie Hao, Xiangrong Huang, Baoyong Chi:
A 26.9-GHz 4-Element Code-Domain Hybrid Beamforming Phased-Array Receiver. A-SSCC 2023: 1-3 - [c62]Ruichang Ma, Haikun Jia, Hongzhuo Liu, Wei Deng, Zhihua Wang, Baoyong Chi:
IEEE ASSCC 2023/ Session 10/ Paper 10.5. A-SSCC 2023: 1-3 - [c61]Angxiao Yan, Wei Deng, Haikun Jia, Shiwei Zhang, Baoyong Chi:
A Transient Enhancement Digital LDO with Adaptive Ripple Cancelation Based on Optimal Compensation Period Approximation. A-SSCC 2023: 1-3 - [c60]Pingda Guan, Haikun Jia, Wei Deng, Ruichang Ma, Huabing Liao, Zhihua Wang, Baoyong Chi:
A 25.0-to-35.9GHz Dual-Layer Quad-Core Dual-Mode VCO with 189.1dBc/Hz FoM and 200.2dBc/Hz FoMT at 1MHz Offset in 65nm CMOS. CICC 2023: 1-2 - [c59]Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Baoyong Chi:
A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS. CICC 2023: 1-2 - [c58]Bufan Zhu, Wei Deng, Ziying Huang, Haikun Jia, Haiyang Jia, Angxiao Yan, Yumeng Yang, Junfeng Liu, Yu Fu, Shiyan Sun, Chao Tang, Taikun Ma, Jiajie Tang, Baoyong Chi:
Transceiver SoC for Wireless Indoor Sensing Data-fusion. CICC 2023: 1-2 - [c57]Hongzhuo Liu, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Baoyong Chi:
A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter. ESSCIRC 2023: 261-264 - [c56]Dongze Li, Wei Deng, Haikun Jia, Ruiheng Qiu, Xintao Li, Ziyuan Guo, Baoyong Chi:
A 37-to-41.8 GHz Double-Gm-Boosting LNA with 2.9-dB NFmin Using Quadruple-Coupling Transformer for Phased-Array Transceivers. ESSCIRC 2023: 385-388 - [c55]Shijie Li, Ruichang Ma, Mingxing Deng, Jiamin Xue, Wei Deng, Baoyong Chi, Haikun Jia:
INVITED PAPER: A 312.5Mbps-32Gbps JESD204C Wireline Transceiver Back-Compatible with JESD204B in 28nm CMOS. ICTA 2023: 21-24 - [c54]Ziying Huang, Wei Deng, Haikun Jia, Bufan Zhu, Angxiao Yan, Baoyong Chi:
A 6.5-to-8GHz IEEE 802.15.4z-compliant All-Digital UWB Transmitter with Integrated Fast-Settling Master-Slave Regulator. ISCAS 2023: 1-4 - [c53]Qixiu Wu, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi:
An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique. ISSCC 2023: 146-147 - [c52]Yumeng Yang, Wei Deng, Angxiao Yan, Haikun Jia, Junlong Gong, Zhihua Wang, Baoyong Chi:
A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration. ISSCC 2023: 228-229 - [c51]Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi:
An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j28]Wei Deng, Zipeng Chen, Haikun Jia, Angxiao Yan, Shiyan Sun, Guopei Chen, Zhihua Wang, Baoyong Chi:
A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation. IEEE J. Solid State Circuits 57(4): 1162-1174 (2022) - [j27]Yaqian Sun, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi:
A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4028-4032 (2022) - [c50]Taikun Ma, Wei Deng, Haikun Jia, Yejun He, Baoyong Chi:
A 76-81 GHz FMCW 2TX/3RX Radar Transceiver with Integrated Mixed-Mode PLL and Series-Fed Patch Antenna Array. ASP-DAC 2022: 3-4 - [c49]Ruichang Ma, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
A 12.5-to-15.4GHz, -118.9dBc/Hz PN at 1MHz offset, and 191.0dBc/Hz FoM VCO with Common-Mode Resonance Expansion and Simultaneous Differential 2ND-Harmonic Output using a Single Three-Coil Transformer in 65nm CMOS. CICC 2022: 1-2 - [c48]Hongzhuo Liu, Wei Deng, Haikun Jia, Shiyan Sun, Qixiu Wu, Jiajie Tang, Zhihua Wang, Baoyong Chi:
A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logNdiv. ESSCIRC 2022: 233-236 - [c47]Huabing Liao, Haikun Jia, Xiangrong Huang, Bao Shi, Wei Deng, Baoyong Chi, Zhihua Wang:
A 22.8 GHz to 32.8 GHz Compact Power Amplifier with a 15 dBm Output P1dB and 36.5% Peak PAE in 65-nm CMOS. ICTA 2022: 84-85 - [c46]Qixiu Wu, Wei Deng, Haikun Jia, Rui Wu, Fuyuan Zhao, Baoyong Chi:
A Highly Linearized Ka-band Heterodyne Receiver using a Folded Class-AB Inductive Peaking Mixer and Magnetic-Self-Cancellation-Transformer-Based IF Amplifiers. ISCAS 2022: 3351-3354 - [c45]Haikun Jia, Ruichang Ma, Wei Deng, Zhihua Wang, Baoyong Chi:
A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS. ISSCC 2022: 154-156 - 2021
- [j26]Zheng Sun, Hanli Liu, Hongye Huang, Dexian Tang, Dingxin Xu, Tohru Kaneko, Zheng Li, Jian Pang, Rui Wu, Wei Deng, Atsushi Shirane, Kenichi Okada:
A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 196-209 (2021) - [j25]Bangan Liu, Yuncheng Zhang, Junjun Qiu, Huy Cu Ngo, Wei Deng, Kengo Nakata, Toru Yoshioka, Jun Emmei, Jian Pang, Aravind Tharayil Narayanan, Haosheng Zhang, Teruki Someya, Atsushi Shirane, Kenichi Okada:
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 603-616 (2021) - [c44]Wei Deng, Zheng Song, Ruichang Ma, Haikun Jia, Baoyong Chi:
A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch Antenna. ASP-DAC 2021: 95-96 - [c43]Pingda Guan, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOS. A-SSCC 2021: 1-3 - [c42]Xiangrong Huang, Haikun Jia, Shengnan Dong, Wei Deng, Zhihua Wang, Baoyong Chi:
A 24-30GHz 4-Element Phased Array Transceiver with Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter in 65 nm CMOS Technology. A-SSCC 2021: 1-3 - [c41]Wei Deng, Haikun Jia, Rui Wu, Shiyan Sun, Chenggang Li, Zhihua Wang, Baoyong Chi:
An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator. CICC 2021: 1-2 - [c40]Pingda Guan, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique. CICC 2021: 1-2 - [c39]Xiangrong Huang, Wei Deng, Haikun Jia, Yuhui Wei, Zhihua Wang, Baoyong Chi:
A C-band FMCW Radar Transmitter with a 22 dBm Output Power Series-stacking CMCD PA for Long-distance Detection in 180-nm CMOS Technology. ICTA 2021: 191-192 - [c38]Ziyue Dang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
Optimization methods for high inductance-density inductors for high speed integrated circuits. ICTA 2021: 243-244 - [c37]Haikun Jia, Wei Deng, Pingda Guan, Zhihua Wang, Baoyong Chi:
A 60GHz 186.5dBc/Hz FoM Quad-Core Fundamental VCO Using Circular Triple-Coupled Transformer with No Mode Ambiguity in 65nm CMOS. ISSCC 2021: 298-300 - [c36]Wei Deng, Zipeng Chen, Haikun Jia, Shiyan Sun, Guopei Chen, Zhihua Wang, Baoyong Chi:
A 11.1-to-14.2 GHz Self-adapted Two-point Modulation Dual-path Type-II Digital PLL Concurrently Achieving 124.7-MHz/μs Chirp Rate and 2.27-GHz Bandwidth. VLSI Circuits 2021: 1-2 - [c35]Zipeng Chen, Wei Deng, Haikun Jia, Pingda Guan, Taikun Ma, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, Baoyong Chi:
A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS. VLSI Circuits 2021: 1-2 - 2020
- [j24]Taikun Ma, Wei Deng, Zipeng Chen, Jianxi Wu, Wei Zheng, Shufu Wang, Nan Qi, Yibo Liu, Baoyong Chi:
A CMOS 76-81-GHz 2-TX 3-RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator. IEEE J. Solid State Circuits 55(2): 233-248 (2020) - [j23]Wei Deng, Zheng Song, Ruichang Ma, Jianfu Lin, Yutian Li, Jialiang Ye, Shangcheng Kong, Sanming Hu, Haikun Jia, Baoyong Chi:
An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer. IEEE J. Solid State Circuits 55(8): 2027-2042 (2020) - [j22]Jianxi Wu, Wei Deng, Zipeng Chen, Wei Zheng, Yibo Liu, Shufu Wang, Nan Qi, Baoyong Chi:
A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 60-73 (2020) - [j21]Zipeng Chen, Wei Deng, Haikun Jia, Yibo Liu, Jianxi Wu, Pingda Guan, Jinyu Zhu, Luhong Mao, Zhihua Wang, Baoyong Chi:
A U-Band PLL Using Implicit Distributed Resonators for Sub-THz Wireless Transceivers in 40 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1574-1578 (2020) - [j20]Wei Deng, Rui Wu, Zhijie Chen, Manlai Ding, Haikun Jia, Baoyong Chi:
A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 28(10): 2089-2098 (2020) - [c34]Shengnan Dong, Zipeng Chen, Haikun Jia, Wei Deng, Baoyong Chi:
A 44-52 GHz Reflection-type Phase Shifter with 1.4° Phase Resolution in 28nm CMOS Process. ICTA 2020: 15-16 - [c33]Chenggang Li, Rui Wu, Haikun Jia, Wei Deng, Baoyong Chi:
A 53.1-to-64.5 GHz In-Phase Coupled Quadrature Injection-Locked Oscillator with Transformer-Based I/Q-Phase Differential Injection Scheme. ICTA 2020: 29-30 - [c32]Wei Deng, Rui Wu, Zhijie Chen, Manlai Ding, Baoyong Chi:
A 35-GHz TX and RX CMOS Front-Ends for Ka-Band FMCW Phased-Array Radar Transceivers. ISCAS 2020: 1-4 - [c31]Yaqian Sun, Wei Deng, Baoyong Chi:
A FoM of -191 dB, 4.4-GHz LC-VCO Integrating an 8-Shaped Inductor with an Orthogonal-Coupled Tail-Filtering Inductor. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [j19]Hanli Liu, Atsushi Shirane, Kenichi Okada, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya:
A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. IEEE J. Solid State Circuits 54(12): 3478-3492 (2019) - [c30]Bangan Liu, Yuncheng Zhang, Junjun Qiu, Wei Deng, Zule Xu, Haosheng Zhang, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada:
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. CICC 2019: 1-4 - [c29]Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada:
A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. ISSCC 2019: 256-258 - 2018
- [j18]Hanli Liu, Teerachot Siriburanon, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa:
A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS. IEICE Trans. Electron. 101-C(4): 187-196 (2018) - [j17]Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada:
A Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications. IEEE J. Solid State Circuits 53(12): 3540-3552 (2018) - [j16]Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Zhijie Chen, Wei Deng, Rui Wu, Kenichi Okada:
A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS. IEEE J. Solid State Circuits 53(12): 3672-3687 (2018) - [c28]Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa:
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. CICC 2018: 1-4 - [c27]Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, Tohru Kaneko, Rui Wu, Wei Deng, Kenichi Okada:
A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver. ESSCIRC 2018: 310-313 - [c26]Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada, Akira Matsuzawa:
A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS. ISSCC 2018: 246-248 - [c25]Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Wei Deng, Rui Wu, Kenichi Okada, Akira Matsuzawa:
An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS. ISSCC 2018: 444-446 - 2017
- [j15]Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI. IEICE Trans. Electron. 100-C(3): 259-267 (2017) - [c24]Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ASP-DAC 2017: 13-14 - 2016
- [j14]Dongsheng Yang, Tomohiro Ueno, Wei Deng, Yuki Terashima, Kengo Nakata, Aravind Tharayil Narayanan, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI. IEICE Trans. Electron. 99-C(6): 632-640 (2016) - [j13]Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. IEEE J. Solid State Circuits 51(5): 1246-1260 (2016) - [j12]Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. IEEE J. Solid State Circuits 51(6): 1385-1397 (2016) - [j11]Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB. IEEE J. Solid State Circuits 51(7): 1630-1640 (2016) - [c23]Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. ASP-DAC 2016: 1-2 - [c22]Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. ESSCIRC 2016: 197-200 - 2015
- [j10]Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Rui Wu, Bangan Liu, Kenichi Okada, Akira Matsuzawa:
A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. IEICE Electron. Express 12(15): 20150531 (2015) - [j9]Rui Wu, Wei Deng, Shinji Sato, Takuichi Hirano, Ning Li, Takeshi Inoue, Hitoshi Sakane, Kenichi Okada, Akira Matsuzawa:
A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections. IEICE Trans. Electron. 98-C(4): 304-314 (2015) - [j8]Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit. IEICE Trans. Electron. 98-C(6): 471-479 (2015) - [j7]Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. IEEE J. Solid State Circuits 50(1): 68-80 (2015) - [c21]Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
An HDL-synthesized gated-edge-injection PLL with a current output DAC. ASP-DAC 2015: 2-3 - [c20]Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A tail-current modulated VCO with adaptive-bias scheme. ASP-DAC 2015: 36-37 - [c19]Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. ASP-DAC 2015: 42-43 - [c18]Teerachot Siriburanon, Hanli Liu, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa:
A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. ESSCIRC 2015: 76-79 - [c17]Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB. ESSCIRC 2015: 380-383 - [c16]Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique. ISSCC 2015: 1-3 - [c15]Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. ISSCC 2015: 1-3 - 2014
- [j6]Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. IEEE J. Solid State Circuits 49(1): 50-60 (2014) - [j5]Wei Deng, Shoichi Hara, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios. IEEE J. Solid State Circuits 49(9): 1984-1994 (2014) - [c14]Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. ASP-DAC 2014: 21-22 - [c13]Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. ASP-DAC 2014: 25-26 - [c12]Rui Wu, Qinghong Bu, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A 0.015-mm2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs. A-SSCC 2014: 181-184 - [c11]Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI. A-SSCC 2014: 285-288 - [c10]Aravind Tharayil Narayanan, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz. ESSCIRC 2014: 343-346 - [c9]Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. ISSCC 2014: 266-267 - 2013
- [j4]Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer. IEICE Trans. Electron. 96-C(6): 804-812 (2013) - [j3]Wei Deng, Kenichi Okada, Akira Matsuzawa:
Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing. IEEE J. Solid State Circuits 48(2): 429-440 (2013) - [j2]Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers. IEEE J. Solid State Circuits 48(7): 1710-1720 (2013) - [c8]Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. ASP-DAC 2013: 97-98 - [c7]Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios. ASP-DAC 2013: 99-100 - [c6]Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs. ESSCIRC 2013: 403-406 - [c5]Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits. ISSCC 2013: 248-249 - 2012
- [j1]Wei Deng, Kenichi Okada, Akira Matsuzawa:
A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition. IEICE Trans. Electron. 95-C(7): 1285-1296 (2012) - [c4]Wei Deng, Kenichi Okada, Akira Matsuzawa:
A PVT-robust feedback class-C VCO using an oscillation swing enhancement technique. ASP-DAC 2012: 563-564 - [c3]Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers. ESSCIRC 2012: 201-204 - 2011
- [c2]Wei Deng, Kenichi Okada, Akira Matsuzawa:
An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation. ASP-DAC 2011: 103-104 - [c1]Wei Deng, Kenichi Okada, Akira Matsuzawa:
A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing. ESSCIRC 2011: 499-502
Coauthor Index
[j40] [j39] [j38] [j37] [j36] [j35] [j34] [j33] [c72] [c71] [c70] [c69] [c68] [j32] [j31] [j30] [j29] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [j28] [j27] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [j24] [j23] [j22] [j21] [j20] [c34] [c33] [c32] [c31]
[j40] [j39] [j38] [j37] [j36] [j35] [j34] [j33] [c72] [c71] [c70] [c69] [c68] [j32] [j31] [j30] [j29] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [j28] [j27] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [j23] [j21] [j20] [c34] [c33]
Ken-ichi Okada
aka: Kenichi Okada
aka: Kenichi Okada
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