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2020 – today
- 2024
[c38]Ashwin Prasad
, Sampath Rajendra, Kaushik Rajan, R. Govindarajan, Uday Bondhugula:
SilvanForge: A Schedule-Guided Retargetable Compiler for Decision Tree Inference. SOSP 2024: 488-504- 2023
- [c37]Kingshuk Majumder, Uday Bondhugula:
HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description. ASPLOS (4) 2023: 189-201 - [i9]Kingshuk Majumder, Uday Bondhugula:
Automatic multi-dimensional pipelining for high-level synthesis of dataflow accelerators. CoRR abs/2309.03203 (2023) - 2022
- [c36]Navdeep Katel, Vivek Khandelwal, Uday Bondhugula:
MLIR-based code generation for GPU tensor cores. CC 2022: 117-128 - [c35]Ashwin Prasad, Sampath Rajendra, Kaushik Rajan, R. Govindarajan, Uday Bondhugula:
Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference. MICRO 2022: 494-511 - 2021
- [c34]Chris Lattner, Mehdi Amini, Uday Bondhugula, Albert Cohen, Andy Davis, Jacques A. Pienaar, River Riddle, Tatiana Shpeisman, Nicolas Vasilache, Oleksandr Zinenko:
MLIR: Scaling Compiler Infrastructure for Domain Specific Computation. CGO 2021: 2-14 - [c33]Kumudha Narasimhan, Aravind Acharya, Abhinav Baid, Uday Bondhugula:
A practical tile size selection model for affine loop nests. ICS 2021: 27-39 - [i8]Kingshuk Majumder, Uday Bondhugula:
HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description. CoRR abs/2103.00194 (2021) - [i7]Navdeep Katel, Vivek Khandelwal, Uday Bondhugula:
High Performance GPU Code Generation for Matrix-Matrix Multiplication using MLIR: Some Early Results. CoRR abs/2108.13191 (2021) - 2020
- [j9]Aravind Acharya, Uday Bondhugula, Albert Cohen:
Effective Loop Fusion in Polyhedral Compilation Using Fusion Conflict Graphs. ACM Trans. Archit. Code Optim. 17(4): 26:1-26:26 (2020) - [j8]Karan Aggarwal, Uday Bondhugula:
Optimizing the Linear Fascicle Evaluation Algorithm for Multi-core and Many-core Systems. ACM Trans. Parallel Comput. 7(4): 22:1-22:45 (2020) - [j7]Abhinav Jangda, Uday Bondhugula:
An Effective Fusion and Tile Size Model for PolyMage. ACM Trans. Program. Lang. Syst. 42(3): 12:1-12:27 (2020) - [c32]Suresh Purini, Vinamra Benara, Ziaul Choudhury, Uday Bondhugula:
Bitwidth customization in image processing pipelines using interval analysis and SMT solvers. CC 2020: 167-178 - [i6]Chris Lattner, Jacques A. Pienaar, Mehdi Amini, Uday Bondhugula, River Riddle, Albert Cohen, Tatiana Shpeisman, Andy Davis, Nicolas Vasilache, Oleksandr Zinenko:
MLIR: A Compiler Infrastructure for the End of Moore's Law. CoRR abs/2002.11054 (2020) - [i5]Uday Bondhugula:
High Performance Code Generation in MLIR: An Early Case Study with GEMM. CoRR abs/2003.00532 (2020)
2010 – 2019
- 2019
- [c31]Karan Aggarwal, Uday Bondhugula:
Optimizing the linear fascicle evaluation algorithm for many-core systems. ICS 2019: 425-437 - [i4]Karan Aggarwal, Uday Bondhugula, Varsha Sreenivasan, Devarajan Sridharan:
Optimizing the Linear Fascicle Evaluation Algorithm for Multi-Core and Many-Core Systems. CoRR abs/1905.06234 (2019) - [i3]Kingshuk Majumder, Uday Bondhugula:
A flexible FPGA accelerator for convolutional neural networks. CoRR abs/1912.07284 (2019) - 2018
- [c30]Aravind Acharya, Uday Bondhugula, Albert Cohen:
Polyhedral auto-transformation with no integer linear programming. PLDI 2018: 529-542 - [c29]Abhinav Jangda, Uday Bondhugula:
An effective fusion and tile size model for optimizing image processing pipelines. PPoPP 2018: 261-275 - [i2]Vinamra Benara, Sahithi Rampalli, Ziaul Choudhury, Suresh Purini, Uday Bondhugula:
Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths. CoRR abs/1803.02660 (2018) - [i1]Aravind Acharya, Uday Bondhugula, Albert Cohen:
An Approach for Finding Permutations Quickly: Fusion and Dimension matching. CoRR abs/1803.10726 (2018) - 2017
- [j6]Uday Bondhugula, Vinayaka Bandishti, Irshad Pananilath:
Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations. IEEE Trans. Parallel Distributed Syst. 28(5): 1285-1298 (2017) - [c28]Vinay Vasista, Kumudha Narasimhan, Siddharth Bhat, Uday Bondhugula:
Optimizing geometric multigrid method computation using a DSL approach. SC 2017: 15 - 2016
- [j5]Roshan Dathathri, Ravi Teja Mullapudi, Uday Bondhugula:
Compiling Affine Loop Nests for a Dynamic Scheduling Runtime on Shared and Distributed Memory. ACM Trans. Parallel Comput. 3(2): 12:1-12:28 (2016) - [j4]Somashekaracharya G. Bhaskaracharya, Uday Bondhugula, Albert Cohen:
Automatic Storage Optimization for Arrays. ACM Trans. Program. Lang. Syst. 38(3): 11:1-11:23 (2016) - [j3]Uday Bondhugula, Aravind Acharya, Albert Cohen:
The Pluto+ Algorithm: A Practical Approach for Parallelization and Locality Optimization of Affine Loop Nests. ACM Trans. Program. Lang. Syst. 38(3): 12:1-12:32 (2016) - [c27]Nitin Chugh, Vinay Vasista, Suresh Purini, Uday Bondhugula:
A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs. PACT 2016: 327-338 - [c26]Somashekaracharya G. Bhaskaracharya, Uday Bondhugula, Albert Cohen:
SMO: an integrated approach to intra-array and inter-array storage optimization. POPL 2016: 526-538 - 2015
- [j2]Irshad Pananilath, Aravind Acharya, Vinay Vasista, Uday Bondhugula:
An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations. ACM Trans. Archit. Code Optim. 12(2): 14:1-14:23 (2015) - [c25]Ravi Teja Mullapudi, Vinay Vasista, Uday Bondhugula:
PolyMage: Automatic Optimization for Image Processing Pipelines. ASPLOS 2015: 429-443 - [c24]Aravind Acharya, Uday Bondhugula:
PLUTO+: near-complete modeling of affine transformations for parallelism and locality. PPoPP 2015: 54-64 - 2014
- [c23]Uday Bondhugula, Vinayaka Bandishti, Albert Cohen, Guillain Potron, Nicolas Vasilache:
Tiling and optimizing time-iterated computations on periodic domains. PACT 2014: 39-50 - [c22]Chandan Reddy, Uday Bondhugula:
Effective automatic computation placement and dataallocation for parallelization of regular programs. ICS 2014: 13-22 - 2013
- [j1]Thejas Ramashekar, Uday Bondhugula:
Automatic data allocation and buffer management for multi-GPU machines. ACM Trans. Archit. Code Optim. 10(4): 60:1-60:26 (2013) - [c21]Roshan Dathathri, Chandan Reddy, Thejas Ramashekar, Uday Bondhugula:
Generating efficient data movement code for heterogeneous architectures with distributed-memory. PACT 2013: 375-386 - [c20]Somashekaracharya G. Bhaskaracharya, Uday Bondhugula:
PolyGLoT: A Polyhedral Loop Transformation Framework for a Graphical Dataflow Language. CC 2013: 123-143 - [c19]Uday Bondhugula:
Compiling affine loop nests for distributed-memory parallel architectures. SC 2013: 33:1-33:12 - 2012
- [c18]Vinayaka Bandishti, Irshad Pananilath, Uday Bondhugula:
Tiling stencil computations to maximize parallelism. SC 2012: 40 - 2011
- [c17]Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan, Nicolas Vasilache:
Loop transformations: convexity, pruning and optimization. POPL 2011: 549-562 - 2010
- [c16]Uday Bondhugula, Oktay Günlük, Sanjeeb Dash, Lakshminarayanan Renganarayanan:
A model for fusion and code motion in an automatic parallelizing compiler. PACT 2010: 343-352 - [c15]Rajesh Bordawekar, Uday Bondhugula, Ravi Rao:
Believe it or not!: mult-core CPUs can match GPU performance for a FLOP-intensive application! PACT 2010: 537-538 - [c14]Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan:
Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework. SC 2010: 1-11
2000 – 2009
- 2009
- [c13]Qingda Lu, Christophe Alias, Uday Bondhugula, Thomas Henretty, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan, Yongjian Chen, Haibo Lin, Tin-Fook Ngai:
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors. PACT 2009: 348-357 - [c12]Muthu Manikandan Baskaran, Nagavijayalakshmi Vydyanathan, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan:
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors. PPoPP 2009: 219-228 - [c11]Lakshminarayanan Renganarayanan, Uday Bondhugula, Salem Derisavi, Alexandre E. Eichenberger, Kevin O'Brien:
Compact multi-dimensional kernel extraction for register tiling. SC 2009 - 2008
- [c10]Uday Bondhugula, Muthu Manikandan Baskaran, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan:
Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model. CC 2008: 132-146 - [c9]Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan:
A compiler framework for optimization of affine loop nests for gpgpus. ICS 2008: 225-234 - [c8]Uday Bondhugula, Muthu Manikandan Baskaran, Albert Hartono, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan:
Towards effective automatic parallelization for multicore systems. IPDPS 2008: 1-5 - [c7]Uday Bondhugula, Albert Hartono, J. Ramanujam, P. Sadayappan:
A practical automatic polyhedral parallelizer and locality optimizer. PLDI 2008: 101-113 - [c6]Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan:
Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories. PPoPP 2008: 1-10 - 2007
- [c5]Sriram Krishnamoorthy, Muthu Manikandan Baskaran, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan:
Effective automatic parallelization of stencil computations. PLDI 2007: 235-244 - [c4]Uday Bondhugula, J. Ramanujam, P. Sadayappan:
Automatic mapping of nested loops to FPGAS. PPoPP 2007: 101-111 - 2006
- [c3]Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan:
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths. FCCM 2006: 152-164 - [c2]Uday Bondhugula, Ananth Devulapalli, Joseph Fernando, Pete Wyckoff, P. Sadayappan:
Parallel FPGA-based all-pairs shortest-paths in a directed graph. IPDPS 2006 - 2005
- [c1]Sayantan Sur, Uday Bondhugula, Amith R. Mamidala, Hyun-Wook Jin, Dhabaleswar K. Panda:
High Performance RDMA Based All-to-All Broadcast for InfiniBand Clusters. HiPC 2005: 148-157
Coauthor Index
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last updated on 2024-12-02 21:26 CET by the dblp team
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