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2020 – today
- 2024
[j28]Stefano Bertazzoni
, Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò:
Design Space Exploration for Edge Machine Learning Featured by MathWorks FPGA DL Processor: A Survey. IEEE Access 12: 9418-9439 (2024)- [j27]Lorenzo Canese, Gian Carlo Cardarilli, Riccardo La Cesa, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Sergio Spanò:
A Novel Digital Equalizer Based on RF Sampling Beyond GHz. IEEE Access 12: 92560-92572 (2024) - [j26]Deepa Perumal, Aravindhan Alagarsamy, Sundarakannan Mahilmaran, Gian Carlo Cardarilli, Seok-Bum Ko:
Probability-based mapping approach for an application-aware networks-on-chip architectures. Nano Commun. Networks 41: 100526 (2024) - 2023
- [j25]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Alberto Nannarelli, Sergio Spanò:
An RNS-Based Initial Absolute Position Estimator for Electrical Encoders. IEEE Access 11: 98586-98595 (2023) - [j24]Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Sergio Spanò:
Efficient Digital Implementation of a Multirate-Based Variable Fractional Delay Filter for Wideband Beamforming. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 2231-2235 (2023) - [c105]Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò:
A Hardware-Oriented QAM Demodulation Method Driven by AW-SOM Machine Learning. ACSSC 2023: 937-941 - [c104]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Riccardo La Cesa, Alberto Nannarelli, Marco Re:
Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers. ACSSC 2023: 1547-1551 - [c103]Damiano Angeloni, Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Sergio Spanò:
A RISC-V Hardware Accelerator for Q-Learning Algorithm. ApplePies 2023: 74-79 - [i2]Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Stefania Perri, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke:
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. CoRR abs/2306.15552 (2023) - 2022
- [j23]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Andrea Ricci, Sergio Spanò:
An FPGA-based multi-agent Reinforcement Learning timing synchronizer. Comput. Electr. Eng. 99: 107749 (2022) - [j22]Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Hamed Famil Ghadakchi, Marco Re, Sergio Spanò:
Sensing and Detection of Traffic Signs Using CNNs: An Assessment on Their Performance. Sensors 22(22): 8830 (2022) - [j21]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Massimo Petricca, Marco Re:
Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation. IEEE Trans. Emerg. Top. Comput. 10(1): 186-198 (2022) - [c102]D. Errico, Marco Re, V. Colombo, Gian Carlo Cardarilli, M. Martina, M. Ruo Roch:
AI-Based Sound Event Detection on IoT Nodes: Requirements Evaluation. ApplePies 2022: 141-148 - [c101]Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò:
Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators. ApplePies 2022: 242-247 - [c100]Sergio Spanò, Lorenzo Canese, Gian Carlo Cardarilli:
Profiling of CNNs using the MATLAB FPGA-based Deep Learning Processor. PRIME 2022: 121-124 - [c99]Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò:
FPGA-Based Road Crack Detection Using Deep Learning. SYSINT 2022: 65-73 - 2021
- [j20]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Massimo Panella, Marco Re, Antonello Rosato, Sergio Spanò:
A Parallel Hardware Implementation for 2-D Hierarchical Clustering Based on Fuzzy Logic. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1428-1432 (2021) - [j19]Daniele Giardino, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re, Sergio Spanò:
M-PSK Demodulator With Joint Carrier and Timing Recovery. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 1912-1916 (2021) - [c98]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Dario Natale, Marco Re, Sergio Spanò:
"MR Q-Learning" Algorithm for Efficient Hardware Implementations. ACSCC 2021: 1186-1190 - [c97]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Matteo Guadagno, Marco Re, Sergio Spanò:
A M-PSK Timing Recovery Loop Based on Q-Learning. ApplePies 2021: 39-44 - [c96]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Riccardo La Cesa, Marco Re:
Design and FPGA Implementation of a Low Power OFDM Transmitter for Narrow-Band IoT. SYSTEM 2021: 60-65 - 2020
- [j18]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò:
AW-SOM, an Algorithm for High-Speed Learning in Hardware Self-Organizing Maps. IEEE Trans. Circuits Syst. II Express Briefs 67-II(2): 380-384 (2020) - [j17]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re, Sergio Spanò:
N-Dimensional Approximation of Euclidean Distance. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 565-569 (2020) - [c95]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re, Sergio Spanò:
FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems. ACSSC 2020: 116-120 - [c94]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Marco Re, Sergio Spanò:
An Action-Selection Policy Generator for Reinforcement Learning Hardware Accelerators. ApplePies 2020: 267-272
2010 – 2019
- 2019
- [j16]Marco Matta, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Alberto Nannarelli, Marco Re, Sergio Spanò:
A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer. IEEE Access 7: 124147-124157 (2019) - [j15]Sergio Spanò, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re:
An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm. IEEE Access 7: 186340-186351 (2019) - [c93]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re:
Approximated Canonical Signed Digit for Error Resilient Intelligent Computation. ACSSC 2019: 1616-1620 - [c92]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Marco Re, Sergio Spanò:
Acoustic Emissions Detection and Ranging of Cracks in Metal Tanks Using Deep Learning. ApplePies 2019: 325-331 - [c91]L. Calicchia, V. Ciotoli, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re:
Digital Signal Processing Accelerator for RISC-V. ICECS 2019: 703-706 - 2018
- [j14]Amirhossein Fereidountabar, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari:
Channel estimation for high speed unmanned aerial vehicle with STBC in MIMO radio links. Int. J. Comput. Vis. Robotics 8(3): 318-335 (2018) - [c90]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re:
A Power Efficient Digital Front-End for Cognitive Radio Systems. ACSSC 2018: 199-202 - [c89]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Marco Re, Francesca Silvestri, Sergio Spanò:
Efficient Ensemble Machine Learning Implementation on FPGA Using Partial Reconfiguration. ApplePies 2018: 253-259 - [c88]Gian Carlo Cardarilli, Daniele Giardino, Marco Matta, Marco Re, Francesca Silvestri, Lorenzo Simone, Sergio Spanò:
Comparison and Implementation of Variable Fractional Delay Filters for Wideband Digital Beamforming. ApplePies 2018: 445-451 - [c87]Marco Ottavi, Dario Asciolla, Tiziano Fiorucci, Elena Grosso, Carla Marzullo, Alessandro Scaramella, Simone Stramaccioni, Alessia Zibecchi, Carla Andreani, Gian Carlo Cardarilli, Carlo Cazzaniga, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Pedro Reviriego, Gianluca Furano, Roberto Senesi:
Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility. DTIS 2018: 1-4 - [c86]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Dario Gelfusa, Marco Matta, Alberto Nannarelli, Marco Re, Lorenzo Simone, Sergio Spanò:
Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker. SMACD 2018: 1-20 - [i1]Simone Acciarito, Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Rocco Fazzolari, Gaurav Mani Khanal, Marco Re, Gianluca Susi:
Hardware design of LIF with Latency neuron model with memristive STDP synapses. CoRR abs/1804.00149 (2018) - 2017
- [j13]Simone Acciarito, Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Rocco Fazzolari, Gaurav Mani Khanal, Marco Re, Gianluca Susi:
Hardware design of LIF with Latency neuron model with memristive STDP synapses. Integr. 59: 81-89 (2017) - [c85]Gian Carlo Cardarilli, Luca Di Nunzio, Federico Massimi, Rocco Fazzolari, Carlo De Petris, Giuseppe Augugliaro, Canio Mennuti:
A Wireless Sensor Node for Acoustic Emission Non-destructive Testing. ApplePies 2017: 1-7 - [c84]Francesca Silvestri, Simone Acciarito, Gian Carlo Cardarilli, Gaurav Mani Khanal, Luca Di Nunzio, Rocco Fazzolari, Marco Re:
FPGA Implementation of a Low-Power QRS Extractor. ApplePies 2017: 9-15 - [c83]Simone Acciarito, Gian Carlo Cardarilli, Gaurav Mani Khanal, Marco Matta, Marco Re, Francesca Silvestri, Sergio Spanò, Dario Gelfusa, Lorenzo Simone:
Digital Architecture of Next Generation Spacecraft Tracker Based on Wideband ∆DOR. ApplePies 2017: 17-24 - [c82]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Luca Gerardi, Marco Re, Giovanni Campolo, Domenico Cascone:
A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements. ISCAS 2017: 1-4 - [c81]Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli, Luca Di Nunzio, M. Spaziani Brunella, Rocco Fazzolari, F. Carbonari:
Robust throughput boosting for low latency dynamic partial reconfiguration. SoCC 2017: 86-90 - 2016
- [c80]A. Esposito, Andrea Lomuscio, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re:
Dynamically-loaded Hardware Libraries (HLL) technology for audio applications. ACSSC 2016: 882-886 - [c79]Gaurav Mani Khanal, Simone Acciarito, Gian Carlo Cardarilli, Abhishek Chakraborty, Luca Di Nunzio, Rocco Fazzolari, Alessandro Cristini, Gianluca Susi, Marco Re:
ZnO-rGO Composite Thin Film Resistive Switching Device: Emulating Biological Synapse Behavior. ApplePies 2016: 117-123 - [c78]Simone Acciarito, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Gaurav Mani Khanal, Marco Re:
Compressive Sensing Reconstruction for Complex System: A Hardware/Software Approach. ApplePies 2016: 192-200 - [c77]Filippo Giuliani, Marco Ottavi, Gian Carlo Cardarilli, Marco Re, Luca Di Nunzio, Rocco Fazzolari, Antimo Bruno, Francesco Zuliani:
Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams. DFT 2016: 111-114 - [c76]Andrea Lomuscio, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re:
A hardware framework for on-chip FPGA acceleration. ISIC 2016: 1-4 - 2015
- [j12]Amirhossein Fereidountabar, Gian Carlo Cardarilli, Marco Re:
High Dynamic Optimized Carrier Loop Improvement for Tracking Doppler Rates. J. Electr. Comput. Eng. 2015: 679505:1-679505:6 (2015) - [c75]Simone Acciarito, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re:
A Wireless Sensor Node Based on Microbial Fuel Cell. ApplePies 2015: 143-150 - [c74]Gian Carlo Cardarilli, Leonardo Di Carlo, Alberto Nannarelli, Federico Maria Pandolfi, Marco Re:
A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration. ISSPIT 2015: 291-296 - [c73]Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re:
Characterization of RNS multiply-add units for power efficient DSP. MWSCAS 2015: 1-4 - 2014
- [c72]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re:
TDES cryptography algorithm acceleration using a reconfigurable functional unit. ICECS 2014: 419-422 - [c71]Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re:
Twenty years of research on RNS for DSP: Lessons learned and future perspectives. ISIC 2014: 436-439 - 2013
- [c70]Gian Carlo Cardarilli, Marco Re, Ilir Shuli, Lorenzo Simone:
Compressive sensing spectrum analysis for space autonomous radio receivers. ACSSC 2013: 492-494 - [c69]Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Marco Re, Mario Salerno, Gianluca Susi:
Spiking neural networks based on LIF with latency: Simulation and synchronization effects. ACSSC 2013: 1838-1842 - [c68]Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re:
Truncated multipliers through power-gating for degrading precision arithmetic. ACSSC 2013: 2172-2176 - [c67]Gian Carlo Cardarilli, Marco Re, Ilir Shuli:
High Performance Bit-Stream Decompressor for Partial Reconfigurable FPGAs. ApplePies 2013: 133-140 - [c66]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Salvatore Pontarelli, Marco Re:
A Reconfigurable Functional Unit for Modular Operations. ApplePies 2013: 141-152 - 2012
- [j11]Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano:
Optimized Implementation of RNS FIR Filters Based on FPGAs. J. Signal Process. Syst. 67(3): 201-212 (2012) - [c65]Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re:
Imprecise arithmetic for low power image processing. ACSCC 2012: 983-987 - [c64]Massimo Petricca, Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re:
Power efficient design of parallel/serial FIR filters in RNS. ACSCC 2012: 1015-1019 - [c63]Pietro Albicocco, Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re:
Karatsuba implementation of FIR filters. ACSCC 2012: 1111-1114 - [c62]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Ruby B. Lee:
Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving. ACSCC 2012: 1457-1459 - 2011
- [c61]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re:
Fine-grain Reconfigurable Functional Unit for embedded processors. ACSCC 2011: 488-492 - [c60]Gian Carlo Cardarilli, Marco Re, Ilir Shuli, Lorenzo Simone:
Partial reconfiguration in the implementation of autonomous radio receivers for space. ReCoSoC 2011: 1-6 - 2010
- [c59]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Christian Lenci, Marco Re:
VLSI implementation of reconfigurable cells for RFU in embedded processors. ICECS 2010: 1180-1183 - [c58]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re:
Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit. WISES 2010: 6-11
2000 – 2009
- 2009
- [c57]Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano:
Error Correction Codes for SEU and SEFI Tolerant Memory Systems. DFT 2009: 425-430 - [c56]Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano:
Error detection in addition chain based ECC Point Multiplication. IOLTS 2009: 192-194 - [c55]Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re:
Arithmetic/Logic Blocks for Fine-grained Reconfigurable Units. ISCAS 2009: 2001-2004 - [c54]Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re:
Speed-up of RISC Processor Computation using ADAPTO. ISCAS 2009: 2229-2232 - [c53]Gian Carlo Cardarilli, Marco Re, Leonardo Di Carlo:
Improved Large-signal Model for Vacuum Triodes. ISCAS 2009: 3006-3009 - 2008
- [j10]Salvatore Pontarelli, Marco Ottavi, Vamsi Vankamamidi, Gian Carlo Cardarilli, Fabrizio Lombardi, Adelio Salsano:
Analysis and Evaluations of Reliability of Reconfigurable FPGAs. J. Electron. Test. 24(1-3): 105-116 (2008) - [j9]Lucia Rita Quitadamo, Maria Grazia Marciani, Gian Carlo Cardarilli, Luigi Bianchi:
Describing Different Brain Computer Interface Systems Through a Unique Model: A UML Implementation. Neuroinformatics 6(2): 81-96 (2008) - [c52]Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re:
Reducing power dissipation in pipelined accumulators. ACSCC 2008: 2098-2102 - [c51]Francesco Iacomacci, Catherine Morlet, Francesca Autelitano, Gian Carlo Cardarilli, Marco Re, Enrico Petrongari, Gino Bogo, Mario Franceschelli:
A Software Defined Radio Architecture for a Regenerative Onboard processor. AHS 2008: 164-171 - [c50]Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano:
A Novel Error Detection and Correction Technique for RNS Based FIR Filters. DFT 2008: 436-444 - [c49]Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
On the use of signed digit arithmetic for the new 6-inputs LUT based FPGAs. ICECS 2008: 602-605 - [c48]Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re:
A full-adder based reconfigurable architecture for fine grain applications: ADAPTO. ICECS 2008: 1304-1307 - [c47]Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano:
Totally Fault Tolerant RNS Based FIR Filters. IOLTS 2008: 192-194 - [c46]Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli:
ADAPTO: full-adder based reconfigurable architecture for bit level operations. ISCAS 2008: 3434-3437 - [c45]Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re:
On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters. VLSI-SoC (Selected Papers) 2008: 174-190 - 2007
- [j8]Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Analysis of Errors and Erasures in Parity Sharing RS Codecs. IEEE Trans. Computers 56(12): 1721-1726 (2007) - [j7]Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Concurrent Error Detection in Reed-Solomon Encoders and Decoders. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 842-846 (2007) - [c44]Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante:
Optimization of Self Checking FIR filters by means of Fault Injection Analysis. DFT 2007: 96-104 - [c43]Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante:
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. IOLTS 2007: 194-196 - [c42]G. L. Bernocchi, Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re:
Low-power adaptive filter based on RNS components. ISCAS 2007: 3211-3214 - 2006
- [j6]Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders. IEEE Trans. Computers 55(5): 534-540 (2006) - [c41]Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Localization of Faults in Radix-n Signed Digit Adders. IOLTS 2006: 178-180 - [c40]Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Concurrent error detection in Reed Solomon decoders. ISCAS 2006 - [c39]Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Fault tolerant design of signed digit based FIR filters. ISCAS 2006 - [c38]Gian Carlo Cardarilli, Andrea Del Re, Marco Re, Lorenzo Simone:
Optimized QPSK modulator for DVB-S applications. ISCAS 2006 - 2005
- [j5]Gian Carlo Cardarilli, Fabrizio Lombardi, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
A Comparative Evaluation of Designs for Reliable Memory Systems. J. Electron. Test. 21(4): 429-444 (2005) - [c37]Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
A Self Checking Reed Solomon Encoder: Design and Analysis. DFT 2005: 111-119 - [c36]Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
FPGA oriented design of parity sharing RS codecs. DFT 2005: 259-265 - [c35]D. Bianchi, Gian Carlo Cardarilli, Andrea Del Re, A. Malatesta, Marco Re:
FPGA implementation of a general purpose HMM processor based on token passing algorithm. ECCTD 2005: 285-288 - [c34]Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Design of a Self Checking Reed Solomon Encoder. IOLTS 2005: 201-202 - [c33]Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re:
Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. ISCAS (2) 2005: 1102-1105 - [c32]Marco Ottavi, Luca Schiano, Fabrizio Lombardi, Salvatore Pontarelli, Gian Carlo Cardarilli:
Evaluating the Data Integrity of Memory Systems by Configurable Markov Models. ISVLSI 2005: 257-259 - 2004
- [c31]Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Data Integrity Evaluations of Reed Solomon Codes for Storage Systems. DFT 2004: 158-164 - [c30]Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities. IOLTS 2004: 141-148 - [c29]Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re:
Low-power implementation of polyphase filters in Quadratic Residue Number system. ISCAS (2) 2004: 725-728 - 2003
- [j4]Gian Carlo Cardarilli, A. Leandri, P. Marinucci, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Design of a fault tolerant solid state mass memory. IEEE Trans. Reliab. 52(4): 476-491 (2003) - [c28]Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker. DFT 2003: 401-408 - [c27]Gian Carlo Cardarilli, Andrea Del Re, Marco Re:
IP based reconfigurable digital platform for satellite communications. ISCAS (2) 2003: 37-40 - [c26]Alberto Nannarelli, Gian Carlo Cardarilli, Marco Re:
Power-delay tradeoffs in residue number system. ISCAS (5) 2003: 413-416 - [c25]Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
A fault tolerant hardware based file system manager for solid state mass memory. ISCAS (5) 2003: 649-652 - 2002
- [j3]Marco Re, Andrea Del Re, Gian Carlo Cardarilli:
Efficient Implementation of a Demultiplexer Based on a Multirate Filter Bank for the Skyplex Satellites DVB System. VLSI Design 15(1): 427-440 (2002) - [c24]Gian Carlo Cardarilli, F. Kaddour, A. Leandri, Marco Ottavi, Salvatore Pontarelli, Raoul Velazco:
Bit Flip Injection in Processor-Based Architectures: A Case Study. IOLTW 2002: 117- - [c23]Salvatore Pontarelli, Gian Carlo Cardarilli, A. Leandri, Marco Ottavi, Marco Re, Adelio Salsano:
A self-checking cell logic block for fault tolerant FPGAs. ISCAS (4) 2002: 477-480 - [c22]Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re:
Power characterization of digital filters implemented on FPGA. ISCAS (5) 2002: 801-804 - 2001
- [c21]Marco Ottavi, Gian Carlo Cardarilli, D. Cellitti, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines. DFT 2001: 403-411 - [c20]Salvatore Pontarelli, Gian Carlo Cardarilli, A. Malvoni, Marco Ottavi, Marco Re, Adelio Salsano:
System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology. DFT 2001: 455-460 - [c19]Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli:
Tradeoffs between residue number system and traditional FIR filters. ISCAS (2) 2001: 305-308 - [c18]Marco Re, Alberto Nannarelli, Gian Carlo Cardarilli, Roberto Lojacono:
FPGA realization of RNS to binary signed conversion architecture. ISCAS (4) 2001: 350-353 - [c17]Marco Ottavi, Gian Carlo Cardarilli, Panfilo Marinucci, Salvatore Pontarelli, Adelio Salsano:
Development of a dynamic routing system for a fault tolerant solid state mass memory. ISCAS (4) 2001: 830-833 - 2000
- [c16]Gian Carlo Cardarilli, Adelio Salsano, P. Marinucci, Marco Ottavi:
A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture. DFT 2000: 173- - [c15]Marcello Salmeri, Marco Re, Enrico Petrongari, Gian Carlo Cardarilli:
A novel bacterial algorithm to extract the rule base from a training set. FUZZ-IEEE 2000: 759-761 - [c14]Marco Re, Marcello Salmeri, Gian Carlo Cardarilli:
A CAD environment for fuzzy systems HW/SW mapping. ISCAS 2000: 221-224 - [c13]Marco Re, Gian Carlo Cardarilli, Andrea Del Re, Roberto Lojacono:
FPGA implementation of a demux based on a multirate filter bank. ISCAS 2000: 353-356 - [c12]Gian Carlo Cardarilli, Panfilo Marinucci, Adelio Salsano:
Development of an evaluation model for the design of fault-tolerant solid state mass memory. ISCAS 2000: 673-676
1990 – 1999
- 1999
- [c11]Stefano Bertazzoni, Gian Carlo Cardarilli, D. Piergentili, Marcello Salmeri, Adelio Salsano, Domenico Di Giovenale, G. C. Grande, P. Marinucci, S. Sperandei, S. Bartalucci, G. Mazzenga, Marco Ricci, V. Bidoli, D. de Francesco, Piergiorgio Picozza, A. Rovelli:
Failure Tests on 64 Mb SDRAM in Radiation Environment. DFT 1999: 158-164 - [c10]Gian Carlo Cardarilli, Stefano Bertazzoni, Marcello Salmeri, Adelio Salsano, P. Marinucci:
Design of Fault-Tolerant Solid State Mass Memory. DFT 1999: 302-310 - [c9]Giuseppe Ferri, Franco Alfonsetti, Gian Carlo Cardarilli, Marco Re:
Bipolar and CMOS low voltage-supply reduced-power voltage followers. ICECS 1999: 1503-1506 - [c8]Alberto L. Sangiovanni-Vincentelli, Marco Re, Luciano Lavagno, Gian Carlo Cardarilli, Roberto Lojacono:
Analysis of the quantization noise effects on the SQNR behaviour in analog to digital conversion. ISCAS (2) 1999: 334-338 - 1998
- [j2]Gian Carlo Cardarilli, Marco Re, Roberto Lojacono:
VLSI implementation of a real time fuzzy processor. J. Intell. Fuzzy Syst. 6(3): 389-401 (1998) - 1996
- [c7]Giuseppe Ferri, Willy Sansen, Gian Carlo Cardarilli:
A low-voltage reduced-power constant-gm rail-to-rail fully differential CMOS op-amp. ICECS 1996: 1170-1173 - 1995
- [c6]Gian Carlo Cardarilli, Gabriele Di Stefano, G. Fabrizi, P. Marinucci:
Analysis and implementation of a VLSI neural network. ICNN 1995: 1482-1486 - 1993
- [c5]Gian Carlo Cardarilli, M. Di Zenzo, Pat O. Pistilli, Adelio Salsano:
A High Speed Reed-Solomon Encoder-Decoder for Fault Tolerant Solid State Disks. DFT 1993: 33-40 - 1992
- [j1]Gian Carlo Cardarilli, Martin Hasler:
Letter limit cycles in residue number system filters. Eur. Trans. Telecommun. 3(5): 479-483 (1992) - [c4]Gian Carlo Cardarilli, Marcello Salmeri, Adelio Salsano:
Grid Generation and Verification for 3-D Device Simulation. EUROSIM 1992: 517-522 - 1990
- [c3]Mario Salerno, Gian Carlo Cardarilli, Roberto Lojacono, F. Sargeni:
RNS approach to full parallel linear combinators. ICASSP 1990: 925-928
1980 – 1989
- 1989
- [c2]Gian Carlo Cardarilli, Roberto Lojacono, Mario Salerno:
RNS approach to fast dividers. ICASSP 1989: 2389-2392 - 1988
- [c1]Pietro Burrascano, Gian Carlo Cardarilli, Roberto Lojacono, Giuseppe Martinelli, Mario Salerno:
RNS Fourier transforms. ICASSP 1988: 1427-1430
Coauthor Index
[j28] [j27] [j25] [j24] [c105] [c104] [c103] [j23] [j22] [j21] [c101] [c99] [j20] [j19] [c98] [c97] [c96] [j18] [j17] [c95] [c94] [j16] [j15] [c93] [c92] [c91] [j14] [c90] [c89] [c87] [c86] [i1] [j13] [c85] [c84] [c82] [c81] [c80] [c79] [c78] [c77] [c75] [c72] [c69] [c66] [c62] [c61] [c59] [c58] [c55] [c54] [c48] [c46]
[j28] [j27] [j25] [j24] [c105] [c104] [c103] [j23] [j22] [j21] [c102] [c101] [c99] [j20] [j19] [c98] [c97] [c96] [j18] [j17] [c95] [c94] [j16] [j15] [c93] [c92] [c91] [c90] [c89] [c88] [c87] [c86] [i1] [j13] [c84] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [c76] [j12] [c75] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [j11] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [j8] [j7] [c44] [c43] [c42] [j6] [c41] [c40] [c39] [c38] [j5] [c37] [c36] [c35] [c34] [c33] [c31] [c30] [c29] [j4] [c28] [c27] [c26] [c25] [j3] [c23] [c22] [c21] [c20] [c19] [c18] [c15] [c14] [c13] [c9] [c8] [j2]
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