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Masaru Sanada

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2000 – 2009

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2008
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Masaru Sanada:
Voltage-based fault path tracing by transistor operating point analysis. Microelectron. Reliab. 48(8-9): 1533-1538 (2008)
2006
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Masaru Sanada, Yutaka Yoshizawa:
Fault diagnosis technology based on transistor behavior analysis for physical analysis. Microelectron. Reliab. 46(9-11): 1575-1580 (2006)
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Yasuo Sato, Kazushi Sugiura, Reisuke Shimoda, Yutaka Yoshizawa, Kenji Norimatsu, Masaru Sanada:
Defect Diagnosis - Reasoning Methodology. ATS 2006: 209-214
2004
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Masaru Sanada:
Layout-Based Detection Technique of Line Pairs with Bridging Fault Using I_DDQ. IEICE Trans. Inf. Syst. 87-D(3): 557-563 (2004)
2001
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Masaru Sanada:
Defect Detection from Visual Abnormalities in Manufacturing Process Using IDDQ. J. Electron. Test. 17(3-4): 275-281 (2001)
2000
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Masaru Sanada:
Defect detection from visual abnormalities in manufacturing process using I_DDQ. ETW 2000: 39-44

1990 – 1999

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1996
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Masaru Sanada:
A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq. VTS 1996: 186-191

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