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ORCIDJames Coole
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2010 – 2019
- 2018
[c7]David Wilson, Greg Stitt, James Coole:
A Recurrently Generated Overlay Architecture for Rapid FPGA Application Development. HEART 2018: 4:1-4:6- 2017
- [c6]Anshuman Verma, Huiyang Zhou
, Skip Booth, Robbie King, James Coole, Andy Keep, John Marshall, Wu-chun Feng:
Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs. DAC 2017: 56:1-56:6 - 2015
- [c5]James Coole, Greg Stitt:
Adjustable-Cost Overlays for Runtime Compilation. FCCM 2015: 21-24 - 2014
- [j4]James Coole, Greg Stitt:
Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts. IEEE Micro 34(1): 42-53 (2014) - 2012
- [c4]James Coole, Greg Stitt:
BPR: fast FPGA placement and routing using macroblocks. CODES+ISSS 2012: 275-284 - 2011
- [j3]Greg Stitt, Alan D. George, Herman Lam, Melissa C. Smith, Vikas Aggarwal, Gongyu Wang, Casey Reardon, Brian Holland, Seth Koehler, James Coole:
An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing. IEEE Des. Test Comput. 28(4): 68-77 (2011) - [j2]Greg Stitt, James Coole:
Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation. IEEE Embed. Syst. Lett. 3(3): 81-84 (2011) - 2010
- [j1]James Coole, Greg Stitt:
Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures. Int. J. Reconfigurable Comput. 2010: 652620:1-652620:16 (2010) - [c3]James Coole, Greg Stitt:
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing. CODES+ISSS 2010: 13-22
2000 – 2009
- 2009
- [c2]James Coole, John Robert Wernsing, Greg Stitt:
A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. ReConFig 2009: 143-148 - 2008
- [c1]Greg Stitt, Gaurav Chaudhari, James Coole:
Traversal caches: a first step towards FPGA acceleration of pointer-based data structures. CODES+ISSS 2008: 61-66
Coauthor Index
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