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ORCIDJun Yu 0010
Person information
- affiliation: Fudan University, State Key Lab of ASIC & System, Shanghai, China
Other persons with the same name
- Jun Yu — disambiguation page
- Jun Yu 0001
![[0000-0002-3197-8103]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-3197-8103")
— University of Science and Technology of China, Department of Automation, Hefei, China - Jun Yu 0002 — Hangzhou Dianzi University, School of Computer Science, China (and 5 more)
- Jun Yu 0003 — Dalian University of Technology, Faculty of Electronic Information and Electrical Engineering, China
- Jun Yu 0004 — Chinese Academy of Sciences, Beijing Institute of Genomics, China (and 1 more)
- Jun Yu 0005 — Umeå University, Umeå, Sweden
- Jun Yu 0006 — Singapore Management University, Singapore, Singapore
- Jun Yu 0007 — Kochi University of Technology, Kami, Japan
- Jun Yu 0008 — London School of Economics and Political Science, London, UK
- Jun Yu 0009 — Li Ka Shing Institute of Health Sciences, Hong Kong, China (and 1 more)
- Jun Yu 0011 — Zhengzhou University of Light Industry, College of Computer and Communication Engineering, China (and 1 more)
- Jun Yu 0012 — Niigata University, Institute of Science and Technology, Niigata-shi, Japan
Other persons with a similar name
- Jun-Yu Chen
- Junyu Guo 0001 (aka: Jun-Yu Guo 0001) — Southwest Petroleum University, School of Mechatronic Engineering, Chengdu, Sichuan, China (and 1 more)
- Jun-Yu Ma
- Dongjun Yu (aka: Dong-Jun Yu)
- Huajun Yu (aka: Hua-Jun Yu) — disambiguation page
- Jun Ye Yu
- Ya Jun Yu
- Junsang Yu 0001 (aka: Jun-Sang Yoo 0001) — Samsung Advanced Institute of Technology (SAIT), Computer Vision Laboratory, Suwon, South Korea (and 1 more)
- Jun Yue — disambiguation page
- Yujun Zheng 0001 (aka: Yu-Jun Zheng 0001) — Zhejiang University of Technology, Hangzhou, China (and 2 more)
- show all similar names
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2020 – today
- 2024
[j7]Enhao Tang, Shun Li, Ruiqi Chen, Hao Zhou, Yuhanxiao Ma, Haoyang Zhang, Jun Yu, Kun Wang:
Graph-OPU: A Highly Flexible FPGA-Based Overlay Processor for Graph Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 17(4): 58:1-58:33 (2024)- [c44]Hongji Wang, Yueyin Bai, Jun Yu, Kun Wang:
TransFRU: Efficient Deployment of Transformers on FPGA with Full Resource Utilization. ASPDAC 2024: 521-526 - [c43]Zihang Ma, Zeyu Li, Yuanfang Wang, Yu Li, Jun Yu, Kun Wang:
Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference with Novel Booth-Multiplier. ASPDAC 2024: 527-532 - [c42]Manting Zhang, Jialin Cao, Kejia Shi, Keqing Zhao, Genhao Zhang, Jun Yu, Kun Wang:
FNM-Trans: Efficient FPGA-based Transformer Architecture with Full N: M Sparsity. DAC 2024: 191:1-191:6 - [c41]Xuanda Lin, Huinan Tian, Wenxiao Xue, Lanqi Ma, Jialin Cao, Manting Zhang, Jun Yu, Kun Wang:
FLAME: Fully Leveraging MoE Sparsity for Transformer on FPGA. DAC 2024: 248:1-248:6 - [c40]Yueyin Bai, Keqing Zhao, Yang Liu, Hongji Wang, Hao Zhou, Xiaoxing Wu, Jun Yu, Kun Wang:
CSTrans-OPU: An FPGA-based Overlay Processor with Full Compilation for Transformer Networks via Sparsity Exploration. DAC 2024: 263:1-263:6 - [c39]Kejia Shi, Manting Zhang, Keqing Zhao, Xiaoxing Wu, Yang Liu, Jun Yu, Kun Wang:
Fitop-Trans: Maximizing Transformer Pipeline Efficiency through Fixed-Length Token Pruning on FPGA. FPL 2024: 243-249 - 2023
- [j6]Peng Zou, Zhijie Cai, Zhifeng Lin, Chenyue Ma, Jun Yu, Jianli Chen:
Incremental 3-D Global Routing Considering Cell Movement and Complex Routing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 2016-2029 (2023) - [j5]Min Wei, Xingyu Tong, Yuan Wen, Jianli Chen, Jun Yu, Wenxing Zhu, Yao-Wen Chang:
Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs. ACM Trans. Design Autom. Electr. Syst. 28(5): 70:1-70:24 (2023) - [c38]Zhijie Cai, Peng Zou, Zhengtao Wu, Xingyu Tong, Jun Yu, Jianli Chen, Yao-Wen Chang:
PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration. DAC 2023: 1-6 - [c37]Guohao Chen, Zheng Zeng, Benchao Zhu, Jiawei Li, Kun Wang, Jun Yu, Jianli Chen:
Mixed-cell-height Placement with Minimum-Implant-Area and Drain-to-Drain Abutment Constraints. DAC 2023: 1-6 - [c36]Peng Zou, Guohao Chen, Zhifeng Lin, Jun Yu, Jianli Chen:
Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints. DAC 2023: 1-6 - [c35]Yueyin Bai, Hao Zhou, Keqing Zhao, Jianli Chen, Jun Yu, Kun Wang:
Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks. FCCM 2023: 221 - [c34]Yuanfang Wang, Yu Li, Haoyang Zhang, Jun Yu, Kun Wang:
Moth: A Hardware Accelerator for Neural Radiance Field Inference on FPGA. FCCM 2023: 227 - [c33]Ruiqi Chen, Haoyang Zhang, Yuhanxiao Ma, Enhao Tang, Shun Li, Yanxiang Zhu, Jun Yu, Kun Wang:
Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks. FPGA 2023: 49 - [c32]Ruiqi Chen, Haoyang Zhang, Shun Li, Enhao Tang, Jun Yu, Kun Wang:
Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks. FPL 2023: 228-234 - [c31]Yueyin Bai, Hao Zhou, Keqing Zhao, Manting Zhang, Jianli Chen, Jun Yu, Kun Wang:
LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks. FPL 2023: 283-287 - [c30]Ruiqi Chen, Haoyang Zhang, Jun Yu, Kun Wang:
FPGA Accelerating Multi-Source Transfer Learning with GAT for Bioactivities of Ligands Targeting Orphan G Protein-Coupled Receptors. FPL 2023: 317-321 - [c29]Yang Liu, Xiaoming He, Jun Yu, Kun Wang:
DIF-LUT: A Simple Yet Scalable Approximation for Non-Linear Activation Function on FPGA. FPL 2023: 322-326 - [c28]Yueyin Bai, Hao Zhou, Ruiqi Chen, Kuangjie Zou, Jialin Cao, Haoyang Zhang, Jianli Chen, Jun Yu, Kun Wang:
g-BERT: Enabling Green BERT Deployment on FPGA via Hardware-Aware Hybrid Pruning. ICC 2023: 1706-1711 - [c27]Yueyin Bai, Hao Zhou, Keqing Zhao, Hongji Wang, Jianli Chen, Jun Yu, Kun Wang:
FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks. ICCAD 2023: 1-9 - [c26]Jialin Cao, Xuanda Lin, Manting Zhang, Kejia Shi, Jun Yu, Kun Wang:
PP-Transformer: Enable Efficient Deployment of Transformers Through Pattern Pruning. ICCAD 2023: 1-9 - [c25]Ruiqi Chen, Haoyang Zhang, Yu Li, Runzhou Zhang, Guoyu Li, Jun Yu, Kun Wang:
Edge FPGA-based Onsite Neural Network Training. ISCAS 2023: 1-5 - [c24]Ruiqi Chen, Haoyang Zhang, Yuhanxiao Ma, Jianli Chen, Jun Yu, Kun Wang:
eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric Sparse Matrix-Vector Multiplication. ISCAS 2023: 1-5 - [c23]Xinyi Xie, Kun Jiang, Rui Dai, Jun Lu, Lihui Wang, Qing Li, Jun Yu:
Access Your Tesla without Your Awareness: Compromising Keyless Entry System of Model 3. NDSS 2023 - 2022
- [j4]Zhifeng Lin, Yanyue Xie, Peng Zou, Sifei Wang, Jun Yu, Jianli Chen:
An Incremental Placement Flow for Advanced FPGAs With Timing Awareness. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 3092-3103 (2022) - [j3]Xiqiong Bai, Ziran Zhu, Pingping Li, Jianli Chen, Tingshen Lan, Xingquan Li, Jun Yu, Wenxing Zhu, Yao-Wen Chang:
Timing-Aware Fill Insertions With Design-Rule and Density Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3529-3542 (2022) - [c22]Xiqiong Bai, Ziran Zhu, Peng Zou, Jianli Chen, Jun Yu, Yao-Wen Chang:
Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. ASP-DAC 2022: 172-177 - [c21]Huimin Wang, Xingyu Tong, Chenyue Ma, Runming Shi, Jianli Chen, Kun Wang, Jun Yu, Yao-Wen Chang:
CNN-inspired analytical global placement for large-scale heterogeneous FPGAs. DAC 2022: 637-642 - [c20]Ruiqi Chen, Yuhanxiao Ma, Shaodong Zheng, Shizhen Huang, Chao Chen, Jun Yu, Kun Wang:
Biological Activity Prediction of GPCR-targeting Ligands on Heterogeneous FPGA-based Accelerators. FCCM 2022: 1 - [c19]Luchang Ding, Chang Cai, Gengsheng Chen, Zehao Wu, Jing Zhang, Chang Wu, Jun Yu:
Characterization of Single Event Upsets of Nanoscale FDSOI Circuits Based on the Simulation and Irradiation Results. ISCAS 2022: 2281-2285 - [c18]Chang Cai, Zehao Wu, Jing Zhang, Luchang Ding, Lei Shen, Jun Yu, Yaqing Chi:
Implementation of Radiation Hardened Flip-Flops Based on Novel Fishbone Layouts. ISCAS 2022: 2286-2289 - 2021
- [c17]Chang Cai, Luchang Ding, Ze He, Jian Yu, Jie Liu, Jiyuan Bai, Gengsheng Chen, Jun Yu:
Simulation of SEU Response of Advanced 20 nm FDSOI SRAMs. ASICON 2021: 1-4 - [c16]Chenyue Ma, Yifeng Xiao, Sifei Wang, Jun Yu, Jianli Chen:
CongestNN: An Bi-Directional Congestion Prediction Framework for Large-Scale Heterogeneous FPGAs. ASICON 2021: 1-4 - [c15]Huimin Wang, Xingyu Tong, Runming Shi, Sifei Wang, Jun Yu, Jianli Chen:
Analytical Global Placement for Heterogenous FPGAs Based on the eDensity Model. ASICON 2021: 1-4 - [c14]Yifeng Xiao, Miaodi Su, Haoyu Yang, Jianli Chen, Jun Yu, Bei Yu:
Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration. DAC 2021: 907-912 - [c13]Zhipeng Huang, Haokai Sun, Huimin Wang, Ziran Zhu, Jun Yu, Jianli Chen:
Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints. DAC 2021: 1362-1363 - [c12]Peng Zou, Zhifeng Lin, Chenyue Ma, Jun Yu, Jianli Chen:
Late Breaking Results: Incremental 3D Global Routing Considering Cell Movement. DAC 2021: 1366-1367 - [c11]Jianli Chen, Jiarui Chen, Xiao Shi, Lichong Sun, Jun Yu:
Late Breaking Results: Novel Discrete Dynamic Filled Function Algorithm for Acyclic Graph Partitioning. DAC 2021: 1368-1369 - [c10]Zhifeng Lin, Yanyue Xie, Gang Qian, Jianli Chen, Sifei Wang, Jun Yu, Yao-Wen Chang:
Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints. DATE 2021: 1564-1569 - 2020
- [c9]Jianli Chen, Zhipeng Huang, Ye Huang, Wenxing Zhu, Jun Yu, Yao-Wen Chang:
An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells *. DAC 2020: 1-6 - [c8]Zhifeng Lin, Yanyue Xie, Gang Qian, Sifei Wang, Jun Yu, Jianli Chen:
Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs*. DAC 2020: 1-2 - [c7]Peng Zou, Zhifeng Lin, Xiao Shi, Yingjie Wu, Jianli Chen, Jun Yu, Yao-Wen Chang:
Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification. DAC 2020: 1-6
2010 – 2019
- 2019
- [j2]Liewei Xu, Chang Cai, Tianqi Liu, Lingyun Ke, Jun Yu, Chang Wu:
Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits. IEICE Electron. Express 16(10): 20190196 (2019) - [c6]Weijun Shan, Jun Yu, Limin Guo, Kun Jiang, Lihui Wang, Qing Li:
A Horizontal Attack on SM9 Signature Generation. CIS 2019: 306-309 - [c5]Jianli Chen, Wenxing Zhu, Jun Yu, Lei He, Yao-Wen Chang:
Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs. ICCAD 2019: 1-8 - [c4]Tingshen Lan, Xingquan Li, Jianli Chen, Jun Yu, Lei He, Senhua Dong, Wenxing Zhu, Yao-Wen Chang:
Timing-Aware Fill Insertions with Design-Rule and Density Constraints. ICCAD 2019: 1-8 - 2018
- [j1]Kun Wang, Jun Yu, Yan Yu, Yirou Qian, Deze Zeng, Song Guo, Yong Xiang, Jinsong Wu:
A Survey on Energy Internet: Architecture, Approach, and Emerging Technologies. IEEE Syst. J. 12(3): 2403-2416 (2018) - 2015
- [c3]Lihui Wang, Qing Li, Gang Zhang, Jun Yu, Zhimin Zhang, Limin Guo, David Wei Zhang:
A New SPA Attack on ECC with Regular Point Multiplication. CIS 2015: 322-325 - [c2]Limin Guo, Lihui Wang, Dan Liu, Weijun Shan, Zhimin Zhang, Qing Li, Jun Yu:
A Chosen - Plaintext Differential Power Analysis Attack on HMAC - SM3. CIS 2015: 350-353 - [c1]Limin Guo, Lihui Wang, Qing Li, Jun Yu, Peng Luo:
Differential Power Analysis on Dynamic Password Token Based on SM3 Algorithm, and Countermeasures. CIS 2015: 354-357
Coauthor Index
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