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ORCIDSandeep Kumar Goel
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2020 – today
- 2024
[c42]Sandeep Kumar Goel, Ankita Patidar, Frank Lee:
Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Impact. ETS 2024: 1-4- [c41]Sandeep Kumar Goel, Moiz Khan, Ankita Patidar, Frank Lee, Vuong Nguyen, Bharath Shankaranarayanan, Doo Kim, Manish Arora:
Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests. ITC 2024: 51-55 - [c40]Sandeep Kumar Goel, Ankita Patidar, Moiz Khan, Frank Lee, Anshuman Chandra, Martin Keim, Naim Lemar, Jonathan Gaudet, Quoc Phan, Vidya Neerkundar:
Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard. ITC 2024: 451-459 - 2023
- [c39]Anshuman Chandra, Moiz Khan, Ankita Patidar, Fumiaki Takashima, Sandeep Kumar Goel, Bharath Shankaranarayanan, Vuong Nguyen, Vistrita Tyagi, Manish Arora:
A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation. ITC 2023: 11-20 - 2022
- [c38]Sandeep Kumar Goel:
Challenges and Solutions for 3D Fabric: A Foundry Perspective. ISPD 2022: 93 - [c37]Sandeep Kumar Goel, Sandeep Pendharkar, Chunsheng Liu:
Innovative Practices Track: Test of 3D ICs & Chiplets. VTS 2022: 1 - 2020
- [j10]Mu-Shan Lin
, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Ching-Fang Chen, Wen-Hung Huang, Chi-Wei Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee:
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. IEEE J. Solid State Circuits 55(4): 956-966 (2020)
2010 – 2019
- 2019
- [c36]Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Tom Chen, Wen-Hung Huang, Jack Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee:
A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. VLSI Circuits 2019: 28- - 2015
- [j9]Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen:
Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption. IEEE Trans. Computers 64(12): 3335-3347 (2015) - [c35]Zipeng Li, Sandeep Kumar Goel, Frank Lee, Krishnendu Chakrabarty:
Efficient observation-point insertion for diagnosability enhancement in digital circuits. ITC 2015: 1-10 - 2014
- [j8]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2388-2401 (2014) - [c34]Sandeep Kumar Goel, Min-Jer Wang, Saman Adham, Ashok Mehta, Frank Lee:
Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs. VLSI-DAT 2014: 1-4 - [p3]Sandeep Kumar Goel, Narendra Devta-Prasanna:
Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 147-160 - [p2]Sandeep Kumar Goel, Krishnendu Chakrabarty:
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 161-184 - [p1]Narendra Devta-Prasanna, Sandeep Kumar Goel:
Small-Delay Defect Coverage Metrics. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 185-210 - [e1]Sandeep Kumar Goel, Krishnendu Chakrabarty:
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits. CRC Press 2014, ISBN 978-1-439-82941-7 [contents] - 2013
- [c33]Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim:
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. ITC 2013: 1-10 - 2012
- [c32]Erik Jan Marinissen, Gilbert Vandling, Sandeep Kumar Goel, Friedrich Hapke, Jason Rivers, Nikolaus Mittermaier, Swapnil Bahl:
EDA solutions to new-defect detection in advanced process technologies. DATE 2012: 123-128 - [c31]Sandeep Kumar Goel:
Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer track. ICCAD 2012: 273 - [c30]Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen:
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC 2012: 1-10 - 2011
- [j7]Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree:
Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1705-1718 (2011) - [c29]Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel:
Automation of 3D-DfT Insertion. Asian Test Symposium 2011: 395-400 - [c28]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. Asian Test Symposium 2011: 451-456 - [c27]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
DfT Architecture for 3D-SICs with Multiple Towers. ETS 2011: 51-56 - [c26]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. ITC 2011: 1-10 - 2010
- [c25]Sandeep Kumar Goel, Krishnendu Chakrabarty, Mahmut Yilmaz, Ke Peng, Mohammad Tehranipoor:
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. Asian Test Symposium 2010: 307-312 - [c24]Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree:
Test-architecture optimization for TSV-based 3D stacked ICs. ETS 2010: 24-29
2000 – 2009
- 2009
- [j6]Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty:
Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. IEEE Trans. Computers 58(3): 409-423 (2009) - [c23]Narendra Devta-Prasanna, Sandeep Kumar Goel, Arun Gunda, Mark Ward, P. Krishnamurthy:
Accurate measurement of small delay defect coverage of test patterns. ITC 2009: 1-10 - [c22]Sandeep Kumar Goel, Narendra Devta-Prasanna, Mark Ward:
Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study. ITC 2009: 1-10 - [c21]Sandeep Kumar Goel, Narendra Devta-Prasanna, Ritesh P. Turakhia:
Effective and Efficient Test Pattern Generation for Small Delay Defect. VTS 2009: 111-116 - [c20]Ritesh P. Turakhia, Mark Ward, Sandeep Kumar Goel, Brady Benware:
Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study. VTS 2009: 167-172 - 2007
- [j5]Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez:
Efficient testing and diagnosis of faulty power switches in SOCs. IET Comput. Digit. Tech. 1(3): 230-236 (2007) - [i1]Sandeep Kumar Goel, Erik Jan Marinissen:
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. CoRR abs/0710.4687 (2007) - 2006
- [c19]Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke:
Fault detection and diagnosis with parity trees for space compaction of test responses. DAC 2006: 1095-1098 - [c18]Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. DATE 2006: 285-290 - [c17]Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez:
Testing and Diagnosis of Power Switches in SOCs. ETS 2006: 145-150 - 2005
- [c16]Sandeep Kumar Goel, Erik Jan Marinissen:
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. DATE 2005: 44-49 - [c15]Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen:
Test scheduling for modular SOCs in an abort-on-fail environment. ETS 2005: 8-13 - 2004
- [c14]Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel:
Automatic generation of breakpoint hardware for silicon debug. DAC 2004: 514-517 - [c13]Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk:
Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. DATE 2004: 108-113 - [c12]Ludovic A. Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre:
User-constrained test architecture design for modular SOC testing. ETS 2004: 80-85 - [c11]Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. ITC 2004: 1203-1212 - 2003
- [j4]Sandeep Kumar Goel, Bart Vermeulen:
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. J. Electron. Test. 19(4): 407-416 (2003) - [j3]Sandeep Kumar Goel, Erik Jan Marinissen:
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. J. Electron. Test. 19(4): 425-435 (2003) - [j2]Sandeep Kumar Goel, Erik Jan Marinissen:
SOC test architecture design for efficient utilization of test bandwidth. ACM Trans. Design Autom. Electr. Syst. 8(4): 399-429 (2003) - [c10]Sandeep Kumar Goel, Erik Jan Marinissen:
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. DATE 2003: 10738-10741 - [c9]Sandeep Kumar Goel, Erik Jan Marinissen:
Control-aware test architecture design for modular SOC testing. ETW 2003: 57-62 - 2002
- [j1]Bart Vermeulen, Sandeep Kumar Goel:
Design for Debug: Catching Design Errors in Digital Chips. IEEE Des. Test Comput. 19(3): 37-45 (2002) - [c8]Sandeep Kumar Goel, Erik Jan Marinissen:
A novel test time reduction algorithm for test architecture design for core-based system chips. ETW 2002: 7-12 - [c7]Sandeep Kumar Goel, Bart Vermeulen:
Data invalidation analysis for scan-based debug on multiple-clock system chips. ETW 2002: 61-66 - [c6]Sandeep Kumar Goel, Erik Jan Marinissen:
Effective and Efficient Test Architecture Design for SOCs. ITC 2002: 529-538 - [c5]Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel:
Core-Based Scan Architecture for Silicon Debug. ITC 2002: 638-647 - [c4]Sandeep Kumar Goel, Bart Vermeulen:
Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. ITC 2002: 1103-1110 - [c3]Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. ITC 2002: 1159-1168 - [c2]Sandeep Kumar Goel, Erik Jan Marinissen:
Cluster-Based Test Architecture Design for System-on-Chip. VTS 2002: 259-264 - 2000
- [c1]Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel:
Wrapper design for embedded core test. ITC 2000: 911-920
Coauthor Index
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last updated on 2024-12-11 20:46 CET by the dblp team
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