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ORCIDGabriel M. Silberman
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2010 – 2019
- 2012
[c16]Ethan Hadar, Irit Hadar, Gabriel M. Silberman, John J. Harrison Jr.:
The 4x6 Tiered Architecture Method: An Approach to the Design of Enterprise Solutions. CAiSE Workshops 2012: 180-191
2000 – 2009
- 2008
- [c15]Ethan Hadar, Gabriel M. Silberman:
Agile architecture methodology: long term strategy interleaved with short term tactics. OOPSLA Companion 2008: 641-652 - 2003
- [j23]Michael A. Bauer, Gene F. Hoffnagle, J. Howard Johnson, Gabriel M. Silberman:
Introduction. Inf. Syst. Frontiers 5(2): 127-128 (2003) - 2002
- [j22]Michael A. Bauer, Gene F. Hoffnagle, J. Howard Johnson, Gabriel M. Silberman:
Introduction. Inf. Syst. Frontiers 4(4): 359-361 (2002) - 2001
- [c14]Leon J. Osterweil, Gabriel M. Silberman, Kenny Wong:
New Software Engineering Faculty Symposium. ICSE 2001: 813
1990 – 1999
- 1997
- [j21]Stephen G. Perelgut, Gabriel M. Silberman, Kelly A. Lyons, Karen Bennet:
Overview: The Centre for Advanced Studies. IBM Syst. J. 36(4): 474-488 (1997) - [j20]Walid A. Najjar, Gabriel M. Silberman:
Foreword to the special issues. Int. J. Parallel Program. 25(4): 243-244 (1997) - 1996
- [j19]Gabriel M. Silberman:
The Third International Conference on Parallel Computing Technologies (PaCT-95), Saint Petersburg, Russia. ACM SIGPLAN Notices 31(2): 8-9 (1996) - 1994
- [j18]Gabriel M. Silberman, Ilan Y. Spillinger:
A backtracing-oriented procedure for the analysis of combinational gate-level designs. Integr. 17(3): 271-286 (1994) - [c13]Kemal Ebcioglu, Randy D. Groves, Ki-Chang Kim, Gabriel M. Silberman, Isaac Ziv:
VLIW Compilation Techniques in a Superscalar Environment. PLDI 1994: 36-48 - [e1]Michel Cosnard, Guang R. Gao, Gabriel M. Silberman:
Parallel Architectures and Compilation Techniques, Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT'94, Montréal, Canada, 24-26 August, 1994. IFIP Transactions A-50, North-Holland 1994, ISBN 0-444-81926-6 [contents] - 1993
- [j17]Gabriel M. Silberman, Kemal Ebcioglu:
An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures. Computer 26(6): 39-56 (1993) - [j16]Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman:
Architectural Improvement for a Data-Driven VLSI Processing Array. J. Parallel Distributed Comput. 19(4): 308-322 (1993) - 1992
- [c12]Gabriel M. Silberman, Kemal Ebcioglu:
An architectural framework for migration from CISC to higher performance platforms. ICS 1992: 198-215 - 1991
- [j15]Gabriel M. Silberman, Ilan Y. Spillinger:
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation. IEEE Trans. Computers 40(1): 66-79 (1991) - [j14]Gabriel M. Silberman, Ilan Y. Spillinger:
RIDDLE: A Foundation for Test Generation on a High-Level Design Description. IEEE Trans. Computers 40(1): 80-87 (1991) - 1990
- [j13]Gabriel M. Silberman, Ilan Y. Spillinger:
Using functional fault simulation and the difference fault model to estimate implementation fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1335-1343 (1990)
1980 – 1989
- 1989
- [j12]Raphael Renous, Gabriel M. Silberman, Ilan Y. Spillinger:
Whistle: A Workbench for Test Development of Library-Based Designs. Computer 22(4): 27-41 (1989) - [c11]Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman:
Architectural Improvements for Data-Driven VLSI Processing Arrays. FPCA 1989: 243-259 - 1988
- [j11]Israel Koren, Bilha Mendelson, Irit Peled, Gabriel M. Silberman:
A Data-Driven VLSI Array for Arbitrary Algorithms. Computer 21(10): 30-43 (1988) - [j10]Paul Erdös, Israel Koren, Shlomo Moran, Gabriel M. Silberman, Shmuel Zaks:
Minimum-Diameter Cyclic Arrangements in Mapping Data-Flow Graphs onto VLSI Arrays. Math. Syst. Theory 21(2): 85-98 (1988) - [j9]Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman:
SLS-a fast switch-level simulator [for MOS]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8): 838-849 (1988) - [c10]Gabriel M. Silberman, Ilan Y. Spillinger:
RIDDLE: a foundation for test generation on a high level design description. FTCS 1988: 76-81 - [c9]Gabriel M. Silberman, Ilan Y. Spillinger:
G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing. ITC 1988: 764-772 - 1987
- [j8]Michael Granski, Israel Koren, Gabriel M. Silberman:
The Effect of Operation Scheduling on the Performance of a Data Flow Computer. IEEE Trans. Computers 36(9): 1019-1029 (1987) - [c8]Bilha Mendelson, Gabriel M. Silberman:
An Improved Mapping of Data Flow Programs on a VLSI Array of Processors. ICPP 1987: 871-873 - [c7]Bilha Mendelson, Gabriel M. Silberman:
Mapping Data Flow Programs on a VLSI Array of Processors. ISCA 1987: 72-80 - 1986
- [j7]Ilan Y. Spillinger, Gabriel M. Silberman:
Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(3): 396-404 (1986) - [c6]Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman:
SLS - a fast switch level simulator for verification and fault coverage analysis. DAC 1986: 164-170 - [c5]Gabriel M. Silberman, Ilan Y. Spillinger:
The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage. ITC 1986: 332-339 - [c4]Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman:
Efficient Fault Simulation of CMOS Circuits with Accurate Models. ITC 1986: 520-529 - 1985
- [c3]Zeev Barzilai, Vijay S. Iyengar, Barry K. Rosen, Gabriel M. Silberman:
Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits. ITC 1985: 722-731 - 1984
- [j6]Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo:
Fast Pass-Transistor Simulation for Custom MOS Circuits. IEEE Des. Test 1(1): 71-81 (1984) - [j5]Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman:
Using a Hardware Simulation Engine for Custom MOS Structured Designs. IBM J. Res. Dev. 28(5): 564-571 (1984) - [j4]Dan Gordon, Israel Koren, Gabriel M. Silberman:
Embedding Tree Stuctures in VLlSI Hexagonal Arrays. IEEE Trans. Computers 33(1): 104-107 (1984) - 1983
- [j3]Gabriel M. Silberman:
Stack Processing Techniques in Delayed-Staging Storage Hierarchies. Commun. ACM 26(11): 999-1007 (1983) - [j2]Gabriel M. Silberman:
Delayed-Staging Hierarchy Optimization. IEEE Trans. Computers 32(11): 1029-1037 (1983) - [c2]Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo:
Simulating pass transistor circuits using logic simulation machines. DAC 1983: 157-163 - [c1]Israel Koren, Gabriel M. Silberman:
A Direct Mapping of Algorithms onto VLSI Processing Arrays Based on the Data Flow Approach. ICPP 1983: 335-337 - 1982
- [j1]Gabriel M. Silberman:
Determining Fault Ratios in Multilevel Delayed-Staging Storage Hierarchies. IEEE Trans. Computers 31(4): 305-310 (1982)
Coauthor Index
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