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ORCIDMark Stephenson
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- affiliation: NVIDIA, Austin, TX, USA
- affiliation: IBM Research, Austin, TX, USA
- affiliation (PhD): Massachusetts Institute of Technology, Cambridge, MA, USA
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2020 – today
- 2023
[j6]Mohamed Tarek Ibn Ziad
, Sana Damani, Aamer Jaleel, Stephen W. Keckler, Mark Stephenson:
cuCatch: A Debugging Tool for Efficiently Catching Memory Safety Violations in CUDA Applications. Proc. ACM Program. Lang. 7(PLDI): 124-147 (2023)- 2022
- [c20]Sana Damani, Mark Stephenson, Ram Rangan, Daniel R. Johnson, Rishkul Kulkami, Stephen W. Keckler:
GPU Subwarp Interleaving. HPCA 2022: 1184-1197 - 2021
- [j5]Mark Stephenson, Ram Rangan, Stephen W. Keckler:
Cooperative Profile Guided Optimizations. Comput. Graph. Forum 40(8): 71-83 (2021) - [c19]Mark Stephenson, Ram Rangan:
PGZ: automatic zero-value code specialization. CC 2021: 36-46 - 2020
- [j4]Ram Rangan, Mark W. Stephenson, Aditya Ukarande, Shyam Murthy, Virat Agarwal, Marc Blackstein:
Zeroploit: Exploiting Zero Valued Operands in Interactive Gaming Applications. ACM Trans. Archit. Code Optim. 17(3): 17:1-17:26 (2020) - [c18]Sana Damani, Daniel R. Johnson, Mark Stephenson, Stephen W. Keckler, Eddie Q. Yan, Michael McKeown, Olivier Giroux:
Speculative reconvergence for improved SIMT efficiency. CGO 2020: 121-132 - [i2]Siva Kumar Sastry Hari, Paolo Rech, Timothy Tsai, Mark Stephenson, Arslan Zulfiqar, Michael B. Sullivan, Philip P. Shirvani, Paul Racunas, Joel S. Emer, Stephen W. Keckler:
Estimating Silent Data Corruption Rates Using a Two-Level Model. CoRR abs/2005.01445 (2020) - [i1]Mark W. Stephenson, Ram Rangan:
AZP: Automatic Specialization for Zero Values in Gaming Applications. CoRR abs/2011.10550 (2020)
2010 – 2019
- 2019
- [j3]Neal Clayton Crago, Mark Stephenson, Stephen W. Keckler:
Exposing Memory Access Patterns to Improve Instruction and Memory Efficiency in GPUs. ACM Trans. Archit. Code Optim. 15(4): 45:1-45:23 (2019) - [c17]Oreste Villa, Mark Stephenson, David W. Nellans, Stephen W. Keckler:
NVBit: A Dynamic Binary Instrumentation Framework for NVIDIA GPUs. MICRO 2019: 372-383 - 2018
- [j2]Dani Voitsechov, Arslan Zulfiqar, Mark Stephenson, Mark Gebhart, Stephen W. Keckler:
Software-Directed Techniques for Improved GPU Register File Utilization. ACM Trans. Archit. Code Optim. 15(3): 38:1-38:23 (2018) - 2017
- [c16]Siva Kumar Sastry Hari, Timothy Tsai, Mark Stephenson, Stephen W. Keckler, Joel S. Emer:
SASSIFI: An architecture-level fault injection tool for GPU application resilience evaluation. ISPASS 2017: 249-258 - 2016
- [c15]Gwangsun Kim, Jiyun Jeong, John Kim, Mark Stephenson:
Automatically Exploiting Implicit Pipeline Parallelism from Multiple Dependent Kernels for GPUs. PACT 2016: 341-352 - [c14]Tianhao Zheng, David W. Nellans, Arslan Zulfiqar, Mark Stephenson, Stephen W. Keckler:
Towards high performance paged memory for GPUs. HPCA 2016: 345-357 - 2015
- [c13]Neha Agarwal, David W. Nellans, Mark Stephenson, Mike O'Connor, Stephen W. Keckler:
Page Placement Strategies for GPUs within Heterogeneous Memory Systems. ASPLOS 2015: 607-618 - [c12]Mark Stephenson, Siva Kumar Sastry Hari, Yunsup Lee, Eiman Ebrahimi, Daniel R. Johnson, David W. Nellans, Mike O'Connor, Stephen W. Keckler:
Flexible software profiling of GPU architectures. ISCA 2015: 185-197 - 2014
- [c11]Yunsup Lee, Vinod Grover, Ronny Krashinsky, Mark Stephenson, Stephen W. Keckler, Krste Asanovic:
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures. MICRO 2014: 101-113 - 2013
- [c10]Ramakrishnan Rajamony, Mark W. Stephenson, William Evan Speight:
The power 775 architecture at scale. ICS 2013: 183-192 - [c9]Ignacio Laguna, Edgar A. León, Martin Schulz, Mark Stephenson:
A study of application-level recovery methods for transient network faults. ScalA@SC 2013: 3:1-3:8 - 2010
- [c8]Mark Stephenson, Ram Rangan, Emmanuel Yashchin, Eric Van Hensbergen:
Statistically regulating program behavior via mainstream computing. CGO 2010: 238-247
2000 – 2009
- 2009
- [c7]Mark Stephenson, Lixin Zhang, Ram Rangan:
Lightweight predication support for out of order processors. HPCA 2009: 201-212 - 2007
- [c6]Vipin Sachdeva, Evan Speight, Mark W. Stephenson, Lei Chen:
Characterizing and Improving the Performance of Bioinformatics Workloads on the POWER5 Architecture. IISWC 2007: 89-97 - 2006
- [b1]Mark W. Stephenson:
Automating the construction of a complier heuristics using machine learning. Massachusetts Institute of Technology, Cambridge, MA, USA, 2006 - 2005
- [c5]Mark Stephenson, Saman P. Amarasinghe:
Predicting Unroll Factors Using Supervised Classification. CGO 2005: 123-134 - 2004
- [j1]Diego Puppin, Mark Stephenson, Saman P. Amarasinghe:
Convergent Scheduling. J. Instr. Level Parallelism 6 (2004) - 2003
- [c4]Mark Stephenson, Una-May O'Reilly, Martin C. Martin, Saman P. Amarasinghe:
Genetic Programming Applied to Compiler Heuristic Optimization. EuroGP 2003: 238-253 - [c3]Diego Puppin, Mark Stephenson, Saman P. Amarasinghe, Martin C. Martin, Una-May O'Reilly:
Adapting Convergent Scheduling Using Machine-Learning. LCPC 2003: 17-31 - [c2]Mark Stephenson, Saman P. Amarasinghe, Martin C. Martin, Una-May O'Reilly:
Meta optimization: improving compiler heuristics with machine learning. PLDI 2003: 77-90 - 2000
- [c1]Mark Stephenson, Jonathan Babb, Saman P. Amarasinghe:
Bitwidth analysis with application to silicon compilation. PLDI 2000: 108-120
Coauthor Index
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