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2020 – today
- 2021
[j6]Wei-Ting Chen
, Ren-Der Chen, Pei-Yin Chen, Yu-Che Hsiao:
A High-Performance Bidirectional Architecture for the Quasi-Comparison-Free Sorting Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4): 1493-1506 (2021)
2010 – 2019
- 2015
- [j5]Ren-Der Chen, Pei-Yin Chen, Chun-Hsien Yeh:
A Low-Power Architecture for the Design of a One-Dimensional Median Filter. IEEE Trans. Circuits Syst. II Express Briefs 62-II(3): 266-270 (2015) - 2013
- [j4]Ren-Der Chen, Pei-Yin Chen, Chun-Hsien Yeh:
Design of an Area-Efficient One-Dimensional Median Filter. IEEE Trans. Circuits Syst. II Express Briefs 60-II(10): 662-666 (2013)
2000 – 2009
- 2008
- [j3]Pei-Yin Chen, Ren-Der Chen, Yu-Pin Chang, Leang-San Shieh, Heidar A. Malki:
Hardware Implementation for a Genetic Algorithm. IEEE Trans. Instrum. Meas. 57(4): 699-705 (2008) - 2003
- [j2]Pei-Yin Chen, Ren-Der Chen:
An index coding algorithm for image vector quantization. IEEE Trans. Consumer Electron. 49(4): 1513-1520 (2003) - 2002
- [j1]Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen:
Design of a dynamic pipelined architecture for fuzzy color correction. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 924-929 (2002)
1990 – 1999
- 1999
- [c4]Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau:
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. ASP-DAC 1999: 185-188 - [c3]Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau:
An efficient method for the decomposition and resynthesis of speed-independent circuits. ICECS 1999: 339-342 - 1994
- [c2]Jer-Min Jou, Ren-Der Chen, Shiann-Rong Kuang:
Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. ISCAS 1994: 45-48 - [c1]Jer-Min Jou, Shung-Chih Chen, Ren-Der Chen:
A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits. ISCAS 1994: 85-88
Coauthor Index
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