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ORCIDChien-Hsing Wu 0002
Person information
- affiliation: National Chung Cheng University, Electrical Engineering Department, Chia-Yi, Taiwan
- affiliation (former): National Yunlin University of Science and Technology, Taiwan
- affiliation (former): Chunghwa Telecom Lab, Taiwan
- affiliation (PhD 1993): University of California, Los Angeles, CA, USA
Other persons with the same name
- Chien-Hsing Wu — disambiguation page
- ChienHsing Wu 0001
![[0000-0003-1331-8790]](https://dblp.org/img/orcid-mark.12x12.png "0000-0003-1331-8790")
(aka: Chien-Hsing Wu 0001, James Chien-Hsing Wu) — National University of Kaohsiung, Department of Information Management, Taiwan (and 1 more)
Other persons with a similar name
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2010 – 2019
- 2017
[j4]Chia-Peng Chou, Tsung-Hsien Liu, Chien-Hsing Wu:
Robust Training Symbol Assisted Least Squares Estimation for Direct Conversion Receivers with Oscillator IQ-Imbalance. Wirel. Pers. Commun. 95(2): 1397-1406 (2017)
2000 – 2009
- 2009
- [c12]Chia-Peng Chou, Chien-Hsing Wu, Tsung-Hsien Liu, Yin-Tsung Hwang:
Space-Frequency-Coded MIMO OFDM Receivers Based on Gaussian Message Passing. ICC 2009: 1-4 - 2005
- [j3]Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen:
VLSI architectural design tradeoffs for sliding-window log-MAP decoders. IEEE Trans. Very Large Scale Integr. Syst. 13(4): 439-447 (2005) - [c11]Chien-Hsing Wu, Yan-Chr Tsai, Hwa-Long Tsai:
Quantum circuits for stabilizer codes. ISCAS (3) 2005: 2333-2336 - 2004
- [j2]Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). IEEE Trans. Computers 53(3): 375-380 (2004) - [c10]Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo:
VLSI architecture exploration for sliding-window Log-MAP decoders. ISCAS (2) 2004: 513-516 - 2003
- [c9]Yin-Tsung Hwang, Kuo-Wei Liao, Chien-Hsing Wu:
FPGA realization of an OFDM frame synchronization design for dispersive channels. ISCAS (2) 2003: 256-259 - 2002
- [j1]Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
Novel Algorithms and VLSI Design for Division over GF(2m). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(5): 1129-1139 (2002) - [c8]Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu:
Memory arrangements in turbo decoders using sliding-window BCJR algorithm. ISCAS (5) 2002: 557-560 - [c7]Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
An area-efficient systolic division circuit over GF(2m) for secure communication. ISCAS (5) 2002: 733-736 - 2001
- [c6]Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. ISCAS (4) 2001: 33-36 - [c5]Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu:
VLSI architecture of extended in-place path metric update for Viterbi decoders. ISCAS (4) 2001: 206-209 - 2000
- [c4]Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu:
An efficient approach for in-place scheduling of path metric update in Viterbi decoders. ISCAS 2000: 61-64
1990 – 1999
- 1999
- [c3]Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu:
A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. ISCAS (1) 1999: 500-503 - [c2]Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu:
An area-efficient versatile Reed-Solomon decoder for ADSL. ISCAS (1) 1999: 517-520 - 1995
- [c1]Yin-Hwa Huang, Yuo-Chuan Chang, Chi-Shyan Wu, Chien-Hsing Wu:
Design of an MPEG-based set-top box for video on demand services. ICASSP 1995: 2655-2658
Coauthor Index
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