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Mandalagiri S. Chandrasekhar

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1990 – 1999

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1997
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Mandalagiri S. Chandrasekhar, Robert H. McCharles, David E. Wallace:
Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits. VLSI Design 5(2): 125-140 (1997)
1990
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David E. Wallace, Mandalagiri S. Chandrasekhar:
High-Level Delay Estimation for Technology-Independent Logic Equations. ICCAD 1990: 188-191

1980 – 1989

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1989
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Mandalagiri S. Chandrasekhar, Melvin A. Breuer:
Optimal routing of two rectangular blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(4): 413-430 (1989)
1987
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Mandalagiri S. Chandrasekhar, J. P. Privitera, K. W. Conradt:
Application of Term Rewriting Techniques to Hardware Design Verification. DAC 1987: 277-282
1982
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Mandalagiri S. Chandrasekhar, Melvin A. Breuer:
Optimum placement of two rectangular blocks. DAC 1982: 879-886

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