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2010 – 2019
- 2013
[b1]Ons Mbarek:
An electronic system level modeling approach for the design and verification of low-power systems-on chip. (Une approche de modélisation au niveau système pour la conception et la vérification de systèmes sur puce à faible consommation). University of Nice Sophia Antipolis, France, 2013- [j2]Ons Mbarek, Alain Pegatoquet, Michel Auguin:
Power domain management interface: flexible protocol interface for transaction-level power domain management. IET Comput. Digit. Tech. 7(4): 155-166 (2013) - [c5]Ons Mbarek, Alain Pegatoquet, Michel Auguin, Houssem Eddine Fathallah:
Power-Aware Wrappers for Transaction-Level Virtual Prototypes: A Black Box Based Approach. VLSI Design 2013: 239-244 - 2012
- [j1]Ons Mbarek, Alain Pegatoquet, Michel Auguin:
Using unified power format standard concepts for power-aware design and verification of systems-onchip at transaction level. IET Circuits Devices Syst. 6(5): 287-296 (2012) - [c4]Ons Mbarek, Alain Pegatoquet, Michel Auguin:
Black-box and white-box early power intent simulation and verification: Two novel approaches. DASIP 2012: 1-8 - [c3]Ons Mbarek, Amani Khecharem, Alain Pegatoquet, Michel Auguin:
Using model driven engineering to reliably accelerate early Low Power Intent Exploration for a system-on-chip design. SAC 2012: 1580-1587 - 2011
- [c2]Ons Mbarek, Alain Pegatoquet, Michel Auguin:
A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard Concepts. PATMOS 2011: 226-236
2000 – 2009
- 2009
- [c1]Muhammad Khurram Bhatti
, Muhammad Farooq, Cécile Belleudy, Michel Auguin, Ons Mbarek:
Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems. PATMOS 2009: 116-126
Coauthor Index
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