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ORCIDAlessandro Ottaviano
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2020 – today
- 2024
[j5]Alessandro Ottaviano
, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini:
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation. Int. J. Parallel Program. 52(1-2): 93-123 (2024)- [j4]Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini:
A High-Performance, Energy-Efficient Modular DMA Engine Architecture. IEEE Trans. Computers 73(1): 263-277 (2024) - [j3]Robert Balas, Alessandro Ottaviano, Luca Benini:
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1032-1044 (2024) - [c6]Chaoqun Liang, Alessandro Ottaviano, Thomas Benz, Mattia Sinigaglia, Luca Benini, Angelo Garofalo, Davide Rossi:
A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems. CF (Companion) 2024 - [c5]Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini:
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs. DATE 2024: 1-6 - [c4]Alessandro Ottaviano, Robert Balas, Philippe Sauter, Manuel Eggimann, Luca Benini:
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors. DATE 2024: 1-6 - [c3]Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini:
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems Through Polling-Free and Retry-Free Operation. DATE 2024: 1-6 - [i13]Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini:
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation. CoRR abs/2401.09359 (2024) - [i12]Giovanni Bambini, Alessandro Ottaviano, Christian Conficoni, Andrea Tilli, Luca Benini, Andrea Bartolini:
Modeling and Controlling Many-Core HPC Processors: an Alternative to PID and Moving Average Algorithms. CoRR abs/2405.18030 (2024) - [i11]Chaoqun Liang, Alessandro Ottaviano, Thomas Benz, Mattia Sinigaglia, Luca Benini, Angelo Garofalo, Davide Rossi:
A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems. CoRR abs/2406.06394 (2024) - [i10]Michael Rogenmoser, Alessandro Ottaviano, Thomas Benz, Robert Balas, Matteo Perotti, Angelo Garofalo, Luca Benini:
SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications. CoRR abs/2406.06546 (2024) - [i9]Enrico Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff, Angelo Garofalo, Luca Benini:
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems. CoRR abs/2410.07798 (2024) - [i8]Alessandro Ottaviano, Robert Balas, Tim Fischer, Thomas Benz, Andrea Bartolini, Luca Benini:
ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package. CoRR abs/2410.15985 (2024) - 2023
- [j2]Matteo Perotti, Matheus A. Cavalcante, Alessandro Ottaviano, Jiantao Liu, Luca Benini:
Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3732-3736 (2023) - [j1]Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca Benini:
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3777-3781 (2023) - [c2]Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino:
Towards a RISC-V Open Platform for Next-generation Automotive ECUs. MECO 2023: 1-8 - [i7]Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca Benini:
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In. CoRR abs/2305.04760 (2023) - [i6]Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini:
A High-performance, Energy-efficient Modular DMA Engine Architecture. CoRR abs/2305.05240 (2023) - [i5]Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini:
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation. CoRR abs/2306.09501 (2023) - [i4]Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino:
Towards a RISC-V Open Platform for Next-generation Automotive ECUs. CoRR abs/2307.04148 (2023) - [i3]Robert Balas, Alessandro Ottaviano, Luca Benini:
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers. CoRR abs/2311.08320 (2023) - [i2]Alessandro Ottaviano, Robert Balas, Philippe Sauter, Manuel Eggimann, Luca Benini:
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors. CoRR abs/2311.09645 (2023) - [i1]Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini:
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs. CoRR abs/2311.09662 (2023) - 2022
- [c1]Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Corrado Bonfanti, Simone Benatti, Davide Rossi, Luca Benini, Andrea Bartolini:
ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration. SAMOS 2022: 120-135
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