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ORCIDAlbert R. Wang
Person information
- affiliation: EECS Department, University of California, Berkeley, CA, USA
Other persons with a similar name
- Albert Wang
- Albert C. L. Wang
- Albert Z. Wang
![[0000-0002-0581-5765]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-0581-5765")
(aka: Albert Z. H. Wang) — University of California, Riverside, CA, USA (and 1 more)
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2000 – 2009
- 2001
[c11]Ying Zhao, Sharad Malik, Albert R. Wang, Matthew W. Moskewicz, Conor F. Madigan:
Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. ICCD 2001: 447-452
1990 – 1999
- 1998
- [j9]Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang:
Code Optimization Techniques in Embedded DSP Microprocessors. Des. Autom. Embed. Syst. 3(1): 59-73 (1998) - 1996
- [j8]Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang:
Storage Assignment to Decrease Code Size. ACM Trans. Program. Lang. Syst. 18(3): 235-253 (1996) - 1995
- [c10]Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang:
Code Optimization Techniques for Embedded DSP Microprocessors. DAC 1995: 599-604 - [c9]Peter Vanbekbergen, Albert R. Wang, Kurt Keutzer:
A Design and Validation System for Asynchronous Circuits. DAC 1995: 725-730 - [c8]Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang:
Storage Assignment to Decrease Code Size. PLDI 1995: 186-195 - 1994
- [j7]Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 814-822 (1994) - [j6]Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Certified timing verification and the transition delay of a logic circuit. IEEE Trans. Very Large Scale Integr. Syst. 2(3): 333-342 (1994) - [j5]Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Verification of asynchronous interface circuits with bounded wire delays. J. VLSI Signal Process. 7(1-2): 161-182 (1994) - [c7]Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert R. Wang:
Challenges in code generation for embedded processors. Code Generation for Embedded Processors 1994: 48-64 - 1993
- [j4]Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Computation of floating mode delay in combinational circuits: practice and implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12): 1924-1936 (1993) - 1992
- [c6]Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Certified Timing Verification and the Transition Delay of a Logic Circuit. DAC 1992: 549-555 - [c5]Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Verification of asynchronous interface circuits with bounded wire delays. ICCAD 1992: 188-195
1980 – 1989
- 1989
- [j3]Srinivas Devadas, Albert R. Wang, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Boolean decomposition in multilevel logic optimization. IEEE J. Solid State Circuits 24(2): 399-408 (1989) - [c4]Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Multi-level Logic Simplification Using Don't Cares and Filters. DAC 1989: 277-282 - 1988
- [j2]Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang:
Multi-level logic minimization using implicit don't cares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6): 723-740 (1988) - [c3]Sharad Malik, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Logic verification using binary decision diagrams in a logic synthesis environment. ICCAD 1988: 6-9 - [c2]Kanwar Jit Singh, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Timing optimization of combinational logic. ICCAD 1988: 282-285 - [c1]Srinivas Devadas, Albert R. Wang, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Boolean decomposition in multi-level logic optimization. ICCAD 1988: 290-293 - 1987
- [j1]Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang:
MIS: A Multiple-Level Logic Optimization System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(6): 1062-1081 (1987)
Coauthor Index
aka: Srinivas Devadas
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