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2000 – 2009
- 2005
[j2]Takeo Matsuki, Kazuyoshi Torii, Takeshi Maeda, Yasushi Akasaka, Kiyoshi Hayashi, Naoki Kasai, Tsunetoshi Arikado:
Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs. IEICE Trans. Electron. 88-C(5): 804-810 (2005)
1990 – 1999
- 1996
- [j1]Hiraki Koike, Tetsuya Otsuki, Tohru Kimura, Masao Fukuma, Yoshihiro Hayashi
, Yukihiko Maejima, Kazushi Amanuma, Nobuhira Tanabe, Takeo Matsuki, Shinobu Saito, Tsuneo Takeuchi, Souta Kobayashi, Takemitsu Kunio, Takashi Hase, Yoichi Miyasaka, Nobuaki Shohata, Masahide Takada:
A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme. IEEE J. Solid State Circuits 31(11): 1625-1634 (1996)
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last updated on 2024-12-31 21:39 CET by the dblp team
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