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ORCIDAndrea D'Alessandro
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- Alessandro D'Andrea
- Alessandro Andrea Esposito
![[0000-0001-5534-2620]](https://dblp.org/img/orcid-mark.12x12.png "0000-0001-5534-2620")
(aka: Andrea Esposito 0003) — Ospedale Treviglio-Caravaggio, Department of Radiology, Treviglio, Italy (and 1 more) - Andrea Gasparini (aka: Andrea Alessandro Gasparini) — University of Oslo, Norway
- Andrea Alessandro Ruggiu
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2020 – today
- 2024
[c4]Koichi Kawai, Yuichi Einaga, Yoko Oikawa, Yankang He, Biagio Iorio, Shigekazu Yamada, Yoshihiko Kamata, Tomoko Iwasaki, Andrea D'Alessandro, Erwin Yu, Arvind Muralidharan, Qinge Li, Henry Nguyen, Kim-Fung Chan, Michele Piccardi, Takaaki Ichikawa, Jeff Yu, Guan Wang, Kwangwon Kim, Chulbum Kim, Paolo Mangalindan, Hojung Yun, Luca Nubile, Kapil Verma, Sushanth Bhushan, Dheeraj Srinivasan, Hidehiko Kuge, Rajesh Subramanian, Jiro Kishimoto, Toru Kamijo, Padma Musunuri, Chang Siau, Ramin Ghodsi:
13.7 A 1Tb Density 3b/Cell 3D-NAND Flash on a 2YY-Tier Technology with a 300MB/s Write Throughput. ISSCC 2024: 244-246
2010 – 2019
- 2014
- [c3]Mark Helm, Jae-Kwan Park, Ali Ghalam, Jason Guo, Chang-Wan Ha, Cairong Hu, Heonwook Kim, Kalyan Kavalipurapu, Eric Lee, Ali Mohammadzadeh, Dan Nguyen, Vipul Patel, Ted Pekny, Bill Saiki, Daesik Song, Jeff Tsai, Vimon Viajedor, Luyen Vu, Tinwai Wong, Jung Hee Yun, Ramin Ghodsi, Andrea D'Alessandro, Domenico Di Cicco, Violante Moschiano:
19.1 A 128Gb MLC NAND-Flash device using 16nm planar cell. ISSCC 2014: 326-327 - 2013
- [c2]Giovanni Naso, L. Botticchio, M. Castelli, C. Cerafogli, M. Cichocki, P. Conenna, Andrea D'Alessandro, Luca De Santis, Domenico Di Cicco, W. Di Francesco, M. L. Gallese, Girolamo Gallo, Michele Incarnati, C. Lattaro, Agostino Macerola, G. G. Marotta, Violante Moschiano, D. Orlandi, F. Paolini, S. Perugini, Luigi Pilolli, P. Pistilli, G. Rizzo, F. Rori, Massimo Rossini, Giovanni Santin, Emanuele Sirizotti, A. Smaniotto, U. Siciliani, Marco Tiburzi, R. Meyer, A. Goda, B. Filipiak, Tommaso Vali, Mark Helm, Ramin Ghodsi:
A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology. ISSCC 2013: 218-219 - 2010
- [c1]G. G. Marotta, Agostino Macerola, Andrea D'Alessandro, A. Torsi, C. Cerafogli, C. Lattaro, C. Musilli, D. Rivers, Emanuele Sirizotti, F. Paolini, G. Imondi, G. Naso, Giovanni Santin, L. Botticchio, Luca De Santis, Luigi Pilolli, M. L. Gallese, Michele Incarnati, Marco Tiburzi, P. Conenna, S. Perugini, Violante Moschiano, W. Di Francesco, Matt Goldman, Chris Haid, Domenico Di Cicco, D. Orlandi, F. Rori, Massimo Rossini, Tommaso Vali, Ramin Ghodsi, Frank Roohparvar:
A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s. ISSCC 2010: 444-445
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