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2020 – today
- 2024
[c21]Philip C. Jose, Ying Xu, André van Schaik, Runchun Wang:
An FPGA Implementation of An Event-Driven Unsupervised Feature Extraction Algorithm for Pattern Recognition. ISCAS 2024: 1-5- 2021
- [c20]Samalika Lakmali Perera, Ying Xu, André van Schaik
, Runchun Wang:
Live Demonstration: An FPGA-Based Emulation of an Event-Based Vision Sensor Using Commercially Available Camera. ISCAS 2021: 1 - 2020
- [c19]Tobi Delbrück, Ibrahim Abe M. Elfadel, Shahzad Muzaffar, Germain Haessig, Bo Wang, Amine Bermak, Rui Graca, Luis A. Camuñas-Mesa, Bathiya Senevirathna, Pamela Abshire, Bernabé Linares-Barranco, Saeed Afshar, Shih-Chii Liu, Runchun Mark Wang, Piotr Dudek, Stephen J. Carey, José M. de la Rosa, Marc Dandin, Sheung Lu, Vincent Frick, Teresa Serrano-Gotarredona, Paula López, Melika Payvand, Advait Madhavan, Eric R. Fossum, Juan Camilo Vasquez Tieck, Ian Williams, Yan Liu, Timothy G. Constandinou, Alexander Serb, Ricardo Carmona-Galán, Robert Nawrocki, Walter D. Leon-Salas:
Lessons Learned the Hard Way. ISCAS 2020: 1-18
2010 – 2019
- 2019
- [j5]Ram Kuber Singh, Ying Xu, Runchun Wang, Tara Julia Hamilton, Susan L. Denham, André van Schaik:
CAR-Lite: A Multi-Rate Cochlear Model on FPGA for Spike-Based Sound Encoding. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(5): 1805-1817 (2019) - [c18]Mark D. McDonnell, Hesham Mostafa, Runchun Wang, André van Schaik:
Single-Bit-per-Weight Deep Convolutional Neural Networks without Batch-Normalization Layers for Embedded Systems. ACIRS 2019: 197-204 - [c17]Ying Xu, Saeed Afshar, Ram Kuber Singh, Runchun Wang, André van Schaik, Tara Julia Hamilton:
A Binaural Sound Localization System using Deep Convolutional Neural Networks. ISCAS 2019: 1-5 - [i13]Mark D. McDonnell, Hesham Mostafa, Runchun Wang, André van Schaik:
Single-bit-per-weight deep convolutional neural networks without batch-normalization layers for embedded systems. CoRR abs/1907.06916 (2019) - 2018
- [j4]Chetan Singh Thakur, Runchun Wang, Tara Julia Hamilton, Ralph Etienne-Cummings, Jonathan Tapson, André van Schaik:
An Analogue Neuromorphic Co-Processor That Utilizes Device Mismatch for Learning Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(4): 1174-1184 (2018) - [c16]Ram Kuber Singh, Ying Xu, Runchun Wang, Tara Julia Hamilton, André van Schaik, Susan L. Denham:
CAR-Lite: A Multi-Rate Cochlea Model on FPGA. ISCAS 2018: 1-5 - [c15]Ying Xu, Saeed Afshar, Ram Kuber Singh, Tara Julia Hamilton, Runchun Wang, André van Schaik:
A Machine Hearing System for Binaural Sound Localization based on Instantaneous Correlation. ISCAS 2018: 1-5 - [i12]Runchun Wang, Chetan Singh Thakur, André van Schaik:
An FPGA-based Massively Parallel Neuromorphic Cortex Simulator. CoRR abs/1803.03015 (2018) - [i11]Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, Ralph Etienne-Cummings:
Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain. CoRR abs/1805.08932 (2018) - 2017
- [j3]Runchun Wang, Chetan Singh Thakur, Gregory Cohen, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
Neuromorphic Hardware Architecture Using the Neural Engineering Framework for Pattern Recognition. IEEE Trans. Biomed. Circuits Syst. 11(3): 574-584 (2017) - 2016
- [j2]Chetan Singh Thakur, Runchun Wang, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
A Low Power Trainable Neuromorphic Integrated Circuit That Is Tolerant to Device Mismatch. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 211-221 (2016) - [c14]Runchun Wang, Gregory Cohen, Chetan Singh Thakur, Jonathan Tapson, André van Schaik:
An SRAM-based implementation of a convolutional neural network. BioCAS 2016: 560-563 - [c13]Ying Xu, Chetan Singh Thakur, Ram Kuber Singh, Runchun Wang, Jonathan Tapson, André van Schaik:
Electronic cochlea: CAR-FAC model on FPGA. BioCAS 2016: 564-567 - [c12]Runchun Wang, Chetan Singh Thakur, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
A stochastic approach to STDP. ISCAS 2016: 2082-2085 - [i10]Runchun Wang, Chetan Singh Thakur, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
A Stochastic Approach to STDP. CoRR abs/1603.04080 (2016) - 2015
- [c11]Runchun Wang, Chetan Singh Thakur, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
A compact aVLSI conductance-based silicon neuron. BioCAS 2015: 1-4 - [c10]Ying Xu, Chetan Singh Thakur, Tara Julia Hamilton, Jonathan Tapson, Runchun Wang, André van Schaik:
A reconfigurable mixed-signal implementation of a neuromorphic ADC. BioCAS 2015: 1-4 - [c9]Chetan Singh Thakur, Tara Julia Hamilton, Runchun Wang, Jonathan Tapson, André van Schaik:
A neuromorphic hardware framework based on population coding. IJCNN 2015: 1-8 - [i9]Chetan Singh Thakur, Tara Julia Hamilton, Runchun Wang, Jonathan Tapson, André van Schaik:
A neuromorphic hardware framework based on population coding. CoRR abs/1503.00505 (2015) - [i8]Chetan Singh Thakur, Runchun Wang, Saeed Afshar, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
An Online Learning Algorithm for Neuromorphic Hardware Implementation. CoRR abs/1505.02495 (2015) - [i7]Chetan Singh Thakur, Runchun Wang, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
A Trainable Neuromorphic Integrated Circuit that Exploits Device Mismatch. CoRR abs/1507.02835 (2015) - [i6]Runchun Wang, Chetan Singh Thakur, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
A neuromorphic hardware architecture using the Neural Engineering Framework for pattern recognition. CoRR abs/1507.05695 (2015) - [i5]Runchun Wang, Chetan Singh Thakur, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
A compact aVLSI conductance-based silicon neuron. CoRR abs/1509.00962 (2015) - [i4]Ying Xu, Chetan Singh Thakur, Tara Julia Hamilton, Jonathan Tapson, Runchun Wang, André van Schaik:
A Reconfigurable Mixed-signal Implementation of a Neuromorphic ADC. CoRR abs/1509.00967 (2015) - 2014
- [j1]Shaista Hussain, Arindam Basu, Runchun Mark Wang, Tara Julia Hamilton:
Delay learning architectures for memory and classification. Neurocomputing 138: 14-26 (2014) - [c8]Runchun Wang, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
A compact neural core for digital implementation of the Neural Engineering Framework. BioCAS 2014: 548-551 - [c7]Runchun Wang, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
An FPGA design framework for large-scale spiking neural networks. ISCAS 2014: 457-460 - [c6]Runchun Wang, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
A compact reconfigurable mixed-signal implementation of synaptic plasticity in spiking neurons. ISCAS 2014: 862-865 - [c5]Runchun Wang, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
A generalised conductance-based silicon neuron for large-scale spiking neural networks. ISCAS 2014: 1564-1567 - 2013
- [c4]Runchun Wang, Gregory Cohen, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity. ISCAS 2013: 1592-1595 - [i3]Jonathan Tapson, Gregory Cohen, Saeed Afshar, Klaus M. Stiefel, Y. Buskila, Runchun Wang, Tara Julia Hamilton, André van Schaik:
Synthesis of neural networks for spatio-temporal spike pattern recognition and processing. CoRR abs/1304.7118 (2013) - [i2]Saeed Afshar, Gregory Cohen, Runchun Wang, André van Schaik, Jonathan Tapson, Torsten Lehmann, Tara Julia Hamilton:
The Ripple Pond: Enabling Spiking Networks to See. CoRR abs/1306.3036 (2013) - [i1]Shaista Hussain, Arindam Basu, Runchun Wang, Tara Julia Hamilton:
Delay Learning Architectures for Memory and Classification. CoRR abs/1311.1294 (2013) - 2012
- [c3]Shaista Hussain, Arindam Basu, Runchun Mark Wang, Tara Julia Hamilton:
DELTRON: Neuromorphic architectures for delay based learning. APCCAS 2012: 304-307 - [c2]Runchun Wang, Jonathan Tapson, Tara Julia Hamilton, André van Schaik:
An aVLSI programmable axonal delay circuit with spike timing dependent delay adaptation. ISCAS 2012: 2413-2416 - 2011
- [c1]Runchun Wang, Craig T. Jin, Alistair Lee McEwan, André van Schaik:
A programmable axonal propagation delay circuit for time-delay spiking neural networks. ISCAS 2011: 869-872
Coauthor Index
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