default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMário P. Véstias
Person information
SPARQL queries 
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
[j19]Manuel Augusto M. Vieira, Gonçalo Galvão, Manuela Vieira, Paula Louro, Mário P. Véstias, Pedro Vieira:
Enhancing Urban Intersection Efficiency: Visible Light Communication and Learning-Based Control for Traffic Signal Optimization and Vehicle Management. Symmetry 16(2): 240 (2024)- [j18]Miguel Reis
, Mário P. Véstias, Horácio C. Neto:
Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines. ACM Trans. Reconfigurable Technol. Syst. 17(1): 6:1-6:30 (2024) - [c43]Henrique B. Brum, Mário P. Véstias, Horácio C. Neto:
LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization. ARC 2024: 90-105 - [c42]José T. de Sousa, João D. Lopes, Micaela Serôdio, Horácio C. Neto, Mário P. Véstias:
PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. ARITH 2024: 139-146 - [e1]Iouliia Skliarova, Piedad Brox Jiménez, Mário P. Véstias, Pedro C. Diniz:
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 20th International Symposium, ARC 2024, Aveiro, Portugal, March 20-22, 2024, Proceedings. Lecture Notes in Computer Science 14553, Springer 2024, ISBN 978-3-031-55672-2 [contents] - 2023
- [j17]Maria Inês Frutuoso, Horácio C. Neto, Mário P. Véstias, Rui Policarpo Duarte:
Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA. Algorithms 16(3): 141 (2023) - [j16]Pedro F. Durães, Mário P. Véstias:
Smart Embedded System for Skin Cancer Classification. Future Internet 15(2): 52 (2023) - [j15]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. ACM Trans. Reconfigurable Technol. Syst. 16(1): 13:1-13:36 (2023) - 2022
- [j14]Helena Cruz, Mário P. Véstias, José Monteiro, Horácio C. Neto, Rui Policarpo Duarte:
A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. Remote. Sens. 14(5): 1258 (2022) - [j13]David Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto, Mário P. Véstias:
Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 15: 3600-3611 (2022) - 2021
- [j12]Daniel Pestana, Pedro R. Miranda, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa:
A Full Featured Configurable Accelerator for Object Detection With YOLO. IEEE Access 9: 75864-75877 (2021) - [j11]Mário P. Véstias, Horácio C. Neto:
Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor. Algorithms 14(7): 198 (2021) - [j10]João V. Roque, João D. Lopes, Mário P. Véstias, José T. de Sousa:
IOb-Cache: A High-Performance Configurable Open-Source Cache. Algorithms 14(8): 218 (2021) - [j9]Pedro R. Miranda, Daniel Pestana, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa:
Configurable Hardware Core for IoT Object Detection. Future Internet 13(11): 280 (2021) - [j8]Mário P. Véstias:
Efficient Design of Pruned Convolutional Neural Networks on FPGA. J. Signal Process. Syst. 93(5): 531-544 (2021) - 2020
- [j7]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. IEEE Access 8: 107229-107243 (2020) - [j6]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Moving Deep Learning to the Edge. Algorithms 13(5): 125 (2020) - [j5]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocess. Microsystems 77: 103136 (2020) - [j4]José M. P. Nascimento, Mário P. Véstias, Gabriel Martín:
Hyperspectral Compressive Sensing With a System-On-Chip FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 13: 3701-3710 (2020) - [c41]Valter Mário, João D. Lopes, Mário P. Véstias, José T. de Sousa:
Implementing CNNs Using a Linear Array of Full Mesh CGRAs. ARC 2020: 288-297 - [p1]Mário P. Véstias:
Processing Systems for Deep Learning Inference on Edge Devices. Convergence of Artificial Intelligence and the Internet of Things 2020: 213-240
2010 – 2019
- 2019
- [j3]Mário P. Véstias:
A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing. Algorithms 12(8): 154 (2019) - [c40]Ana Gonçalves, Tiago Peres, Mário P. Véstias:
Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs. ARC 2019: 387-401 - [c39]Tiago Peres, Ana Gonçalves, Mário P. Véstias:
Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning. ARC 2019: 402-416 - [c38]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. FPL 2019: 350-353 - [c37]Luís Fiolhais, Fernando M. Gonçalves, Rui Policarpo Duarte, Mário P. Véstias, José T. de Sousa:
Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. ISCAS 2019: 1-5 - 2018
- [j2]Mário P. Véstias, Horácio C. Neto:
Improving the area of fast parallel decimal multipliers. Microprocess. Microsystems 61: 96-107 (2018) - [c36]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. FPL 2018: 399-402 - 2017
- [j1]Horácio C. Neto, Mário P. Véstias:
Decimal addition on FPGA based on a mixed BCD/excess-6 representation. Microprocess. Microsystems 55: 91-99 (2017) - [c35]João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias:
K-means clustering on CGRA. FPL 2017: 1-4 - [c34]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Parallel dot-products for deep learning on FPGA. FPL 2017: 1-4 - 2016
- [c33]Jose Canilho, Mário P. Véstias, Horácio C. Neto:
Multi-core for K-means clustering on FPGA. FPL 2016: 1-4 - [c32]Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias:
XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system. ICRC 2016: 1-7 - 2015
- [c31]Tiago Rodrigues, Mário P. Véstias:
Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA. DSD 2015: 65-71 - [c30]João Pinhão, Wilson José, Horácio C. Neto, Mário P. Véstias:
Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture. DSD 2015: 330-336 - [c29]Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto:
Enhancing stochastic computations via process variation. FPL 2015: 1-7 - [c28]José M. P. Nascimento, Mário P. Véstias, Gabriel Martín:
FPGA-based architecture for hyperspectral unmixing. IGARSS 2015: 1761-1764 - [i2]Mário P. Véstias, Rui Policarpo Duarte, Horácio C. Neto:
Designing Hardware/Software Systems for Embedded High-Performance Computing. CoRR abs/1508.06832 (2015) - 2014
- [c27]Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias:
Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. FPL 2014: 1-4 - [c26]Mário P. Véstias, Horácio C. Neto:
Trends of CPU, GPU and FPGA for high-performance computing. FPL 2014: 1-6 - [i1]Mário P. Véstias, Horácio C. Neto:
A Many-Core Overlay for High-Performance Embedded Computing on FPGAs. CoRR abs/1408.5401 (2014) - 2013
- [c25]Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias:
Analysis of matrix multiplication on high density Virtex-7 FPGA. FPL 2013: 1-4 - [c24]Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto:
A reconfigurable computing architecture using magnetic tunneling junction memories. FPL 2013: 1-2 - [c23]Wilson José, Ana Rita Silva, Mário P. Véstias, Horácio C. Neto:
Design of a massively parallel computing architecture for dense matrix multiplication. LASCAS 2013: 1-4 - [c22]Mário P. Véstias, Horácio C. Neto, Helena Sarmento:
Design of a multiband full-rate ultra-wideband receiver in FPGA. LASCAS 2013: 1-4 - [c21]Horácio C. Neto, Mário P. Véstias:
Very low resource table-based FPGA evaluation of elementary functions. ReConFig 2013: 1-6 - 2012
- [c20]Mário P. Véstias, Horácio C. Neto:
Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm. DSD 2012: 782-788 - [c19]Mário P. Véstias, Horácio C. Neto, Helena Sarmento:
Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs. DSD 2012: 938-945 - [c18]Mário P. Véstias, Horácio C. Neto, Helena Sarmento:
Sliding block Viterbi decoders in FPGA. FPL 2012: 595-598 - [c17]Mário P. Véstias, Helena Sarmento:
Design of an IEEE 802.15.3c baseband processor in FPGA. ICCE-Berlin 2012: 102-106 - [c16]Mário P. Véstias:
Design and test of a MIMO Receiver based on the Alamouti scheme in FPGA. ICCE-Berlin 2012: 107-111 - [c15]Mário P. Véstias, Helena Sarmento:
Tradeoffs in the design of sliding block Viterbi decoders for MB-OFDM UWB systems. ICCE-Berlin 2012: 173-177 - [c14]Victor Silva, Mário P. Véstias, Horácio C. Neto, Jorge R. Fernandes:
Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions. ICECS 2012: 809-812 - [c13]Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto:
A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory. ReConFig 2012: 1-6 - 2011
- [c12]Mário P. Véstias, Horácio C. Neto:
Revisiting the Newton-Raphson Iterative Method for Decimal Division. FPL 2011: 138-143
2000 – 2009
- 2009
- [c11]Victor Silva, Luís Bica Oliveira, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto:
Run-Time Reconfigurable Array Using Magnetic RAM. DSD 2009: 74-81 - [c10]Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias:
Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. DSD 2009: 273-280 - 2008
- [c9]Vítor Silva, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto:
Multiplier-based double precision floating point divider according to the IEEE-754 standard. ARC 2008: 260-265 - [c8]Horácio C. Neto, Mário P. Véstias:
Decimal multiplier on FPGA using embedded binary multipliers. FPL 2008: 197-202 - 2007
- [c7]Mário P. Véstias, Horácio C. Neto:
Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. FPL 2007: 389-394 - 2006
- [c6]Mário P. Véstias, Horácio C. Neto:
Area/Performance Improvement of NoC Architectures. ARC 2006: 193-198 - [c5]Mário P. Véstias, Horácio C. Neto:
Co-synthesis of a configurable SoC platform based on a network on chip architecture. ASP-DAC 2006: 48-53 - [c4]Mário P. Véstias, Horácio C. Neto:
A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. FPL 2006: 1-4 - [c3]Mário P. Véstias, Horácio C. Neto:
Area and performance optimization of a generic network-on-chip architecture. SBCCI 2006: 68-73 - 2003
- [c2]Mário P. Véstias, Horácio C. Neto:
DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. SBCCI 2003: 85- - 2002
- [c1]Mário P. Véstias, Horácio C. Neto:
System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures. IEEE International Workshop on Rapid System Prototyping 2002: 130-137
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-07-18 20:59 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
