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2020 – today
- 2024
[j41]Takumi Komori, Yutaka Masuda, Tohru Ishihara:
Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(1): 3-15 (2024)- [j40]Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara:
Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3): 540-548 (2024) - [j39]Tohru Ishihara:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 17: 1 (2024) - 2023
- [j38]Yutaka Masuda, Yusei Honda, Tohru Ishihara:
Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 514-522 (2023) - [j37]Lingxiao Hou, Yutaka Masuda, Tohru Ishihara:
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 532-541 (2023) - [c76]Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara:
An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits. DATE 2023: 1-2 - [c75]Yusei Honda, Yutaka Masuda, Tohru Ishihara:
Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design. IOLTS 2023: 1-3 - [c74]Tai-Feng Chen, Yutaka Masuda, Tohru Ishihara:
A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design. SOCC 2023: 1-6 - 2022
- [j36]Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto:
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 509-517 (2022) - [j35]Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara:
Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 518-529 (2022) - [c73]Lingxiao Hou, Yutaka Masuda, Tohru Ishihara:
An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers. ASP-DAC 2022: 568-573 - [c72]Naoki Hattori, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi:
Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design. DAC 2022: 1285-1290 - [c71]Taisei Ichikawa, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi:
Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks. ISVLSI 2022: 390-393 - [c70]Akihiko Shinya, Kengo Nozaki, Shota Kita, Tohru Ishihara, Shinji Matsuo, Masaya Notomi:
Energy efficient OEO conversion and its applications to photonic integrated systems. OFC 2022: 1-3 - [c69]Takumi Komori, Yutaka Masuda, Tohru Ishihara:
DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms. RTCSA 2022: 128-137 - [c68]Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera:
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. SOCC 2022: 1-6 - 2021
- [j34]Naoki Hattori, Jun Shiomi, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi:
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1477-1487 (2021) - [j33]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1546-1554 (2021) - [c67]Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto:
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. DATE 2021: 1260-1265 - [c66]Kazuki Yoshisue, Yutaka Masuda, Tohru Ishihara:
Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing. IOLTS 2021: 1-7 - [c65]Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara:
Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing. ISQED 2021: 300-306 - 2020
- [c64]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. ICRC 2020: 95-101 - [c63]Khyati Kiyawat
, Yutaka Masuda, Jun Shiomi, Tohru Ishihara:
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. ISVLSI 2020: 415-421 - [c62]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. ISVLSI 2020: 488-493
2010 – 2019
- 2019
- [j32]Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
A Design Method of a Cell-Based Amplifier for Body Bias Generation. IEICE Trans. Electron. 102-C(7): 565-572 (2019) - [j31]Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1741-1750 (2019) - [j30]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1751-1759 (2019) - [j29]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. Integr. 65: 201-210 (2019) - [c61]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. ASP-DAC 2019: 203-209 - [c60]Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi:
An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. PHOTONICS@SC 2019: 15-21 - 2018
- [j28]Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi:
An Integrated Nanophotonic Parallel Adder. ACM J. Emerg. Technol. Comput. Syst. 14(2): 26:1-26:20 (2018) - [j27]Jun Shiomi, Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera:
Minimum Energy Point Tracking with All-Digital On-Chip Sensors. J. Low Power Electron. 14(2): 227-235 (2018) - [c59]Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi:
Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics. ICRC 2018: 1-8 - [c58]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing. ICRC 2018: 1-6 - [c57]Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera:
Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation. IOLTS 2018: 177-182 - [c56]Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure. PATMOS 2018: 237-242 - [c55]Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera:
Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization. SoCC 2018: 112-117 - 2017
- [j26]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2764-2775 (2017) - [j25]Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera:
A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2776-2784 (2017) - [c54]Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera:
On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator. VLSI-DAT 2017: 1-4 - 2016
- [j24]Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2463-2472 (2016) - [c53]Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. ASP-DAC 2016: 691-696 - [c52]Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi:
An integrated optical parallel adder as a first step towards light speed data processing. ISOCC 2016: 123-124 - [c51]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Variability- and correlation-aware logical effort for near-threshold circuit design. ISQED 2016: 18-23 - [c50]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. PATMOS 2016: 44-49 - [c49]Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera:
Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing. SoCC 2016: 1-6 - 2015
- [j23]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1455-1466 (2015) - [j22]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell. IPSJ Trans. Syst. LSI Des. Methodol. 8: 131-135 (2015) - [j21]Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring. IEEE J. Solid State Circuits 50(11): 2475-2490 (2015) - [c48]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Microarchitectural-level statistical timing models for near-threshold circuit design. ASP-DAC 2015: 87-93 - [c47]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
An energy-efficient on-chip memory structure for variability-aware near-threshold operation. ISQED 2015: 23-28 - [c46]Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera:
Energy reduction by built-in body biasing with single supply voltage operation. ISQED 2015: 181-185 - [c45]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
An impact of process variation on supply voltage dependence of logic path delay variation. VLSI-DAT 2015: 1-4 - 2014
- [j20]Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada:
An Integrated Framework for Energy Optimization of Embedded Real-Time Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2477-2487 (2014) - [c44]Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring. A-SSCC 2014: 45-48 - [c43]Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Variation-aware Flip-Flop energy optimization for ultra low voltage operation. SoCC 2014: 17-22 - [c42]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. SoCC 2014: 42-47 - 2013
- [j19]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2499-2507 (2013) - [j18]Kyungsoo Lee, Tohru Ishihara:
DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2660-2667 (2013) - [j17]Ji Gu, Hui Guo, Tohru Ishihara:
DLIC: Decoded loop instructions caching for energy-aware embedded processors. ACM Trans. Embed. Comput. Syst. 13(1): 6:1-6:26 (2013) - [c41]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Analysis and comparison of XOR cell structures for low voltage circuit design. ISQED 2013: 703-708 - 2012
- [j16]Lovic Gauthier, Tohru Ishihara:
Processor Energy Characterization for Compiler-Assisted Software Energy Reduction. J. Electr. Comput. Eng. 2012: 786943:1-786943:16 (2012) - [c40]Kyungsoo Lee, Tohru Ishihara:
I/O aware task scheduling for energy harvesting embedded systems with PV and capacitor arrays. ESTIMedia 2012: 48-55 - [c39]Ji Gu, Tohru Ishihara, Kyungsoo Lee:
Loop instruction caching for energy-efficient embedded multitasking processors. ESTIMedia 2012: 97-106 - [c38]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
A flexible structure of standard cell and its optimization method for near-threshold voltage operation. ICCD 2012: 235-240 - [c37]Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
A Standard Cell Optimization Method for Near-Threshold Voltage Operations. PATMOS 2012: 32-41 - [c36]Kyungsoo Lee, Tohru Ishihara:
A Dynamic Reconfiguration Technique for PV and Capacitor Arrays to Improve the Efficiency in Energy Harvesting Embedded Systems. SMARTGREENS 2012: 175-182 - [c35]Ji Gu, Tohru Ishihara:
A Case Study of Energy-efficient Loop Instruction Cache Design for Embedded Multitasking Systems. SMARTGREENS 2012: 197-202 - 2011
- [j15]Lovic Gauthier, Tohru Ishihara:
Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2597-2608 (2011) - [j14]Maziar Goudarzi, Tohru Ishihara, Hamid Noori:
Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies. Trans. High Perform. Embed. Archit. Compil. 3: 275-299 (2011) - [c34]Akitoshi Matsuda, Tohru Ishihara:
Developing an integrated verification and debug methodology. DATE 2011: 503-504 - [c33]Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada:
An integrated optimization framework for reducing the energy consumption of embedded real-time applications. ISLPED 2011: 271-276 - [c32]Takumi Okuhira, Tohru Ishihara:
Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits. PATMOS 2011: 237-246 - 2010
- [j13]Tohru Ishihara:
A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2533-2541 (2010) - [j12]Maziar Goudarzi, Tohru Ishihara:
SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1660-1671 (2010) - [j11]Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura:
Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories. J. Signal Process. Syst. 60(2): 211-224 (2010) - [c31]Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada:
Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems. CASES 2010: 157-166 - [c30]Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura:
An RTOS in hardware for energy efficient software-based TCP/IP processing. SASP 2010: 58-63
2000 – 2009
- 2009
- [j10]Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura:
Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion. IPSJ Trans. Syst. LSI Des. Methodol. 2: 189-199 (2009) - [j9]Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura:
An Optimization Technique for Low-Energy Embedded Memory Systems. IPSJ Trans. Syst. LSI Des. Methodol. 2: 239-249 (2009) - [c29]Lovic Gauthier, Tohru Ishihara:
Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories. ESTIMedia 2009: 116-125 - 2008
- [j8]Maziar Goudarzi, Tohru Ishihara:
Value-dependence of SRAM leakage in deca-nanometer technologies. IEICE Electron. Express 5(1): 23-28 (2008) - [j7]Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami:
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. IEICE Trans. Electron. 91-C(4): 410-417 (2008) - [j6]Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara:
Way-Scaling to Reduce Power of Cache with Delay Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3576-3584 (2008) - [j5]Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura:
A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation. Microelectron. J. 39(12): 1797-1808 (2008) - [c28]Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Tohru Ishihara:
A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems. EUC (1) 2008: 206-213 - [c27]Maziar Goudarzi, Tohru Ishihara:
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. ACM Great Lakes Symposium on VLSI 2008: 383-386 - [c26]Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura:
Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI 2008: 403-406 - [c25]Maziar Goudarzi, Tohru Ishihara, Hamid Noori:
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. HiPEAC 2008: 224-239 - [c24]Maziar Goudarzi, Tohru Ishihara:
Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation. ISLPED 2008: 93-98 - [c23]Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara:
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways. ISVLSI 2008: 447-450 - [c22]Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura:
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. PATMOS 2008: 62-71 - [c21]Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato:
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. SASP 2008: 83-88 - 2007
- [j4]Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami:
Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. IEICE Trans. Electron. 90-C(10): 1983-1991 (2007) - [c20]Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura:
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. ASP-DAC 2007: 878-883 - [c19]Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami:
Task scheduling for reliable cache architectures of multiprocessor systems. DATE 2007: 1490-1495 - [c18]Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura:
Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. ESTIMedia 2007: 13-18 - [i1]Tohru Ishihara, Farzan Fallah:
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors. CoRR abs/0710.4703 (2007) - 2006
- [c17]Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah:
An Energy Characterization Framework for Software-Based Embedded Systems. ESTIMedia 2006: 59-64 - [c16]Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto:
A Simulation-Based Soft Error Estimation Methodology for Computer Systems. ISQED 2006: 196-203 - 2005
- [c15]Tohru Ishihara, Farzan Fallah:
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors. DATE 2005: 358-363 - [c14]Tohru Ishihara, Farzan Fallah:
A cache-defect-aware code placement algorithm for improving the performance of processors. ICCAD 2005: 995-1001 - [c13]Tohru Ishihara:
Energy-Efficient Embedded System Design at 90nm and Below - A System-Level Perspective -. ISHPC 2005: 452-465 - [c12]Tohru Ishihara, Farzan Fallah:
A non-uniform cache architecture for low power system design. ISLPED 2005: 363-368 - 2003
- [c11]Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada:
Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE 2003: 41-42 - 2002
- [c10]Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura:
A Power Minimization Technique for Arithmetic Circuits by Cell Selection. ASP-DAC/VLSI Design 2002: 268-273 - [c9]Tohru Ishihara, Kunihiro Asada:
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. ASP-DAC/VLSI Design 2002: 282-287 - 2001
- [j3]Takanori Okuma, Hiroto Yasuura, Tohru Ishihara:
Software Energy Reduction Techniques for Variable-Voltage Processors. IEEE Des. Test Comput. 18(2): 31-41 (2001) - [c8]Tohru Ishihara, Kunihiro Asada:
A system level memory power optimization technique using multiple supply and threshold voltages. ASP-DAC 2001: 456-461 - 2000
- [j2]Akihiko Inoue, Tohru Ishihara, Hiroto Yasuura:
Flexible System LSI for Embedded Systems and Its Optimization Techniques. Des. Autom. Embed. Syst. 5(2): 179-205 (2000) - [c7]Tohru Ishihara, Hiroto Yasuura:
A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. DATE 2000: 617-623
1990 – 1999
- 1999
- [c6]Koji Inoue, Tohru Ishihara, Kazuaki J. Murakami:
Way-predicting set-associative cache for high performance and low energy consumption. ISLPED 1999: 273-275 - [c5]Takanori Okuma, Tohru Ishihara, Hiroto Yasuura:
Real-Time Task Scheduling for a Variable Voltage Processor. ISSS 1999: 24-29 - 1998
- [c4]Tohru Ishihara, Hiroto Yasuura:
Power-Pro: Programmable Power Management Architecture. ASP-DAC 1998: 321-322 - [c3]Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura:
Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE 1998: 855-860 - [c2]Tohru Ishihara, Hiroto Yasuura:
Voltage scheduling problem for dynamically variable voltage processors. ISLPED 1998: 197-202 - 1996
- [c1]Tohru Ishihara, Hiroto Yasuura:
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. ISLPED 1996: 117-120 - 1993
- [j1]Tohru Ishihara, Masakazu Kojima:
On the big Mu in the affine scaling algorithm. Math. Program. 62: 85-93 (1993)
Coauthor Index
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last updated on 2024-08-05 20:22 CEST by the dblp team
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