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ORCIDFeng Yu 0003
Person information
- affiliation: Zhejiang University, College of Biomedical Engineering and Instrument Science, Hangzhou, China
- affiliation (PhD 2007): Zhejiang University, Department of Instrument Engineering, Hangzhou, China
Other persons with the same name
- Feng Yu — disambiguation page
- Feng Yu 0001
![[0000-0002-7379-250X]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-7379-250X")
— Alibaba Group, China (and 1 more) - Feng Yu 0002 — Youngstown State University, Department of Computer Science and Information Systems, Youngstown, OH, USA (and 1 more)
- Feng Yu 0004 — Beijing Academy of Agriculture and Forestry Sciences, Institute of Agricultural Scientech Information, Beijing, China
- Feng Yu 0005 — City University of New York, Graduate Center, New York, NY, USA
- Feng Yu 0006 — Guangxi Normal University, College of Computer Science, Guilin, China (and 2 more)
- Feng Yu 0007 — Beijing University of Posts and Telecommunications, School of Science, Beijing, China
- Feng Yu 0008 — Northeastern University, College of Information Science and Engineering, State Key Laboratory of Synthetical Automation for Process Industries, Shenyang, China
- Feng Yu 0009 — Technical University of Braunschweig, Institute of Semiconductor Technology, Brunswick, Germany
- Feng Yu 0010 — Hangzhou Dianzi University, School of Computer Science and Technology, Key Laboratory of Complex Systems Modeling and Simulation, Hangzhou, China
- Feng Yu 0011 — Chinese Academy of Sciences, Shanghai Advanced Research Institute, Shanghai Synchrotron Radiation Facility, Shanghai, China
- Feng Yu 0012 — Shihezi University, School of Chemistry and Chemical Engineering, Key Laboratory for Green Processing of Chemical Engineering of Xinjiang Bingtuan, Shihezi, China
- Feng Yu 0013 — Nantong University, School of Electrical Engineering, Nantong, China (and 1 more)
- Feng Yu 0014 — Northeastern University, School of Information Science and Engineering, Shenyang, China
- Feng Yu 0015 — Xi'an Technological University, School of Science, Department of Physics, Xi'an, China
- Feng Yu 0016 — University of Central Florida, Department of Mathematics, Orlando, FL, USA
- Feng Yu 0017 — Wuhan Textile University, School of Computer Science and Artificial Intelligence, Engineering Research Center of Hubei Province for Clothing Information, China (and 2 more)
- Feng Yu 0018 — Purdue University, Department of Earth, Atmospheric, and Planetary Sciences, West Lafayette, IN, USA
- Feng Yu 0019 — Chinese Academy of Sciences, Institute of Computing Technology, SKLCA, Beijing, China (and 1 more)
- Feng Yu 0020 — University of Ottawa, School of Information Technology and Engineering, Ottawa, Canada
- Feng Yu 0021 — Harbin University of Commerce, School of Computer and Information Engineering, Harbin, China
- Feng Yu 0022 — Alibaba Cloud Computing Ltd., Hanzhou, China
Other persons with a similar name
- Yufeng Chen (aka: Yu-Feng Chen) — disambiguation page
- Yu Feng — disambiguation page
- Yue Feng
- Xinyu Feng 0001 (aka: Xin-Yu Feng 0001) — Nanjing University, Department of Computer Science and Technology, China (and 3 more)
- Yu Feng 0001 — University of California, Santa Barbara, CA, USA (and 1 more)
- Yu Feng 0002 — Zhejiang University of Technology, College of Information Engineering, Hangzhou, China (and 2 more)
- Yufeng Li (aka: Yu-Feng Li) — disambiguation page
- Yu-Feng Yu (aka: Yufeng Yu) — disambiguation page
- Feng Yue
- Yufeng Zhao (aka: Yu-Feng Zhao) — disambiguation page
- show all similar names
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2020 – today
- 2024
[j42]Hongji Fang, Zhenguo Ma, Feng Yu, Bei Zhao, Bo Zhang:
Optimised Serial Commutator FFT Architecture in Terms of Multiplexers. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 445-449 (2024)- [j41]Yan Pei, Jiahui Xu, Qianhao Chen, Chenhao Wang, Feng Yu, Lisan Zhang, Wei Luo:
DTP-Net: Learning to Reconstruct EEG Signals in Time-Frequency Domain by Multi-Scale Feature Reuse. IEEE J. Biomed. Health Informatics 28(5): 2662-2673 (2024) - 2023
- [j40]Haori Zheng, Qianhao Chen, Feng Yu, Bo Zhang:
General Adaptive Lossless Compression for Multi-Channel Sensor Signals. IEEE Trans. Circuits Syst. II Express Briefs 70(12): 4594-4598 (2023) - [i2]Yan Pei, Jiahui Xu, Qianhao Chen, Chenhao Wang, Feng Yu, Lisan Zhang, Wei Luo:
DTP-Net: Learning to Reconstruct EEG signals in Time-Frequency Domain by Multi-scale Feature Reuse. CoRR abs/2312.09417 (2023) - 2022
- [j39]Binhao He, Meiting Xue, Shubiao Liu, Feng Yu, Weijie Chen:
Resource Efficient Top-K Sorter on FPGA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(9): 1372-1376 (2022) - [j38]Hongji Fang, Bo Zhang, Feng Yu, Bei Zhao, Zhenguo Ma:
A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4533-4537 (2022) - 2021
- [j37]Bo Zhang, Zhenguo Ma, Feng Yu:
A Novel Pipelined Algorithm and Modular Architecture for Non-Square Matrix Transposition. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1423-1427 (2021) - [j36]Wen-Qi Wu, Meiting Xue, Qianjian Xing, Feng Yu:
High-Parallelism Hash-Merge Architecture for Accelerating Join Operation on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2650-2654 (2021) - 2020
- [j35]Meiting Xue, Huan Zhang, Weijun Li, Feng Yu:
Sorting Matrix Architecture for Continuous Data Sequences. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(2): 542-546 (2020) - [j34]Wei Luo, Feng Yu:
Learning longer-term dependencies via grouped distributor unit. Neurocomputing 412: 406-415 (2020) - [j33]Tianqi Zhu, Wei Luo, Feng Yu:
Multi-Branch Convolutional Neural Network for Automatic Sleep Stage Classification with Embedded Stage Refinement and Residual Attention Channel Fusion. Sensors 20(22): 6592 (2020) - [j32]Weijie Chen, Weijun Li, Feng Yu:
A Hybrid Pipelined Architecture for High Performance Top-K Sorting on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 67-II(8): 1449-1453 (2020) - [j31]Meiting Xue, Qianjian Xing, Chen Feng, Feng Yu, Zhen-Guo Ma:
FPGA-Accelerated Hash Join Operation for Relational Databases. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1919-1923 (2020) - [j30]Wen-Qi Wu, Meiting Xue, Tian-Qi Zhu, Zhen-Guo Ma, Feng Yu:
High-Throughput Parallel SRAM-Based Hash Join Architecture on FPGA. IEEE Trans. Circuits Syst. 67-II(11): 2502-2506 (2020) - [j29]Weijie Chen, Weijun Li, Feng Yu:
Modular Pipeline Architecture for Accelerating Join Operation in RDBMS. IEEE Trans. Circuits Syst. 67-II(11): 2662-2666 (2020)
2010 – 2019
- 2019
- [j28]Zhiwei Li, Ting Gong, Zhichao Lin, Hongjian He, Qiqi Tong, Chen Li, Yi Sun, Feng Yu, Jianhui Zhong:
Fast and Robust Diffusion Kurtosis Parametric Mapping Using a Three-Dimensional Convolutional Neural Network. IEEE Access 7: 71398-71411 (2019) - [j27]Wei Luo, Feng Yu:
Recurrent Highway Networks With Grouped Auxiliary Memory. IEEE Access 7: 182037-182049 (2019) - [j26]Huan Zhang, Bei Zhao, Wei-Jun Li, Zhen-Guo Ma, Feng Yu:
Resource-Efficient Parallel Tree-Based Join Architecture on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 111-115 (2019) - [j25]Yunxiang Wang, Zhen-guo Ma, Feng Yu:
Pipelined Algorithm and Modular Architecture for Matrix Transposition. IEEE Trans. Circuits Syst. II Express Briefs 66-II(4): 652-656 (2019) - [i1]Wei Luo, Feng Yu:
Learning Longer-term Dependencies via Grouped Distributor Unit. CoRR abs/1906.08856 (2019) - 2018
- [j24]Min Yuan, Qianjian Xing, Zhen-guo Ma, Feng Yu, Yingke Xu:
A Fused Continuous Floating-Point MAC on FPGA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(9): 1594-1598 (2018) - 2017
- [j23]Wei Zhang, Feng Yu:
Off-the-Grid Compressive Time Delay Estimation via Manifold-Based Optimization. IEEE Commun. Lett. 21(5): 983-986 (2017) - [j22]Wei Zhang, Feng Yu:
Dynamic Parameterized $\ell _{1}$ -Regulation for Single-Snapshot DOA Estimations. IEEE Commun. Lett. 21(10): 2218-2221 (2017) - [j21]Tingting Chen, Weijun Li, Feng Yu, Qianjian Xing:
Modular Serial Pipelined Sorting Architecture for Continuous Variable-Length Sequences with a Very Simple Control Strategy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(4): 1074-1078 (2017) - [j20]Qianjian Xing, Zhen-guo Ma, Feng Yu:
A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(6): 1333-1337 (2017) - [j19]Wei Zhang, Feng Yu:
Parameterized L1-Minimization Algorithm for Off-the-Gird Spectral Compressive Sensing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(9): 2026-2030 (2017) - [j18]Xiubin Mao, Zhen-guo Ma, Feng Yu, Qianjian Xing:
A Continuous-Flow Memory-Based Architecture for Real-Valued FFT. IEEE Trans. Circuits Syst. II Express Briefs 64-II(11): 1352-1356 (2017) - 2016
- [j17]Xinfa Zhang, Feng Yu:
A novel nonlinear equalizer for extending the dynamic range of analog-to-digital converters. IEICE Electron. Express 13(5): 20160039 (2016) - [j16]Bei Zhao, Chen Cheng, Zhen-guo Ma, Feng Yu:
Time Delay Estimation via Co-Prime Aliased Sparse FFT. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2566-2570 (2016) - [j15]Weijun Li, Feng Yu, Zhen-guo Ma:
Efficient Circuit for Parallel Bit Reversal. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 381-385 (2016) - [j14]Xiaobo Yin, Feng Yu, Zhen-guo Ma:
Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths. IEEE Trans. Circuits Syst. II Express Briefs 63-II(8): 803-807 (2016) - 2015
- [j13]Pengcheng Qiu, Feng Yu:
A Combinatorial Aliasing-Based Sparse Fourier Transform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(9): 1968-1972 (2015) - [j12]Jie Zhou, Feng Yu:
A Cloud-Friendly Communication-Optimal Implementation for Strassen's Matrix Multiplication Algorithm. IEICE Trans. Inf. Syst. 98-D(11): 1896-1905 (2015) - [j11]Lin Li, Feng Yu:
Block Region of Interest Method for Real-Time Implementation of Large and Scalable Image Reconstruction. IEEE Signal Process. Lett. 22(11): 1908-1912 (2015) - [j10]Chen Cheng, Feng Yu:
An Optimum Architecture for Continuous-Flow Parallel Bit Reversal. IEEE Signal Process. Lett. 22(12): 2334-2338 (2015) - [j9]Zhen-guo Ma, Xiaobo Yin, Feng Yu:
A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 62-II(9): 876-880 (2015) - [j8]Jinqi Liu, Qianjian Xing, Xiaobo Yin, Xiubin Mao, Feng Yu:
Pipelined Architecture for a Radix-2 Fast Walsh-Hadamard-Fourier Transform Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 62-II(11): 1083-1087 (2015) - [j7]Ze-ke Wang, Xue Liu, Bingsheng He, Feng Yu:
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 973-977 (2015) - 2014
- [j6]Qianjian Xing, Feng Yu, Xiaobo Yin, Bei Zhao:
Radix-R WHT-FFT with Identical Stage-to-Stage Interconnection Pattern. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(5): 1125-1129 (2014) - [j5]Huan He, Feng Yu, Bei Zhao:
Efficient CORDIC-Based Processing Elements in Scalable Complex Matrix Inversion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(5): 1144-1148 (2014) - 2013
- [j4]Feng Yu, Rui-feng Ge, Ze-ke Wang:
Efficient Utilization of Vector Registers to Improve FFT Performance on SIMD Microprocessors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(7): 1637-1641 (2013) - [c1]Ze-ke Wang, Feng Yu, Xue Liu:
Block Processor: A resource-distributed architecture. HPEC 2013: 1-6 - 2012
- [j3]Teng Su, Feng Yu:
A Family of Fast Hadamard-Fourier Transform Algorithms. IEEE Signal Process. Lett. 19(9): 583-586 (2012) - 2011
- [j2]Xue Liu, Feng Yu, Ze-ke Wang:
A pipelined architecture for normal I/O order FFT. J. Zhejiang Univ. Sci. C 12(1): 76-82 (2011) - [j1]Zhen-guo Ma, Feng Yu, Rui-feng Ge, Ze-ke Wang:
An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays. J. Zhejiang Univ. Sci. C 12(4): 323-329 (2011)
Coauthor Index
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