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2000 – 2009
- 2004
[b1]Holger Kropp:
Quellenmodell-Architekturen redundanz-reduzierender Codierungsverfahren aus LUT-basierten FPGAs. University of Hanover, 2004, ISBN 3-18-374610-7, pp. 1-164- 2002
- [c9]Javier Martín-Langerwerf, Carsten Reuter, Holger Kropp, Peter Pirsch:
Benefits of Macro-Based Multi-FPGA Partitioning for Video Processing Applications. IEEE International Workshop on Rapid System Prototyping 2002: 60-65 - 2001
- [c8]Jörn Gause, Carsten Reuter, Holger Kropp, Peter Y. K. Cheung, Wayne Luk:
The Effect of FPGA Granularity on Video Codec Implementations. FCCM 2001: 287-288 - 2000
- [j1]Carsten Reuter, Holger Kropp, Peter Pirsch:
Rapid Prototyping von Videosignalverarbeitungsverfahren (Rapid Prototyping of Video Processing Schemes). Informationstechnik Tech. Inform. 42(3): 5-9 (2000) - [c7]Holger Kropp, Carsten Reuter:
A Mapping Methodology for Code Trees onto LUT-Based FPGAs. FPL 2000: 221-229
1990 – 1999
- 1999
- [c6]Holger Kropp, Carsten Reuter, Matthias Wiege, Tien-Toan Do, Peter Pirsch:
An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes. FPL 1999: 333-338 - 1998
- [c5]Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch:
A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs. FPL 1998: 441-445 - [c4]Holger Kropp, Carsten Reuter, Peter Pirsch:
The Video and Image Processing Emulation System VIPES. International Workshop on Rapid System Prototyping 1998: 170-175 - 1997
- [c3]Tien-Toan Do, Holger Kropp, Markus Schwiegershausen, Peter Pirsch:
Implementation of pipelined multipliers on Xilinx FPGAs. FPL 1997: 51-60 - 1996
- [c2]Markus Schwiegershausen, Holger Kropp, Peter Pirsch:
A system level HW/SW partitioning and optimization tool. EURO-DAC 1996: 120-125 - [c1]Holger Kropp, Markus Schwiegershausen, Peter Pirsch:
A CAD tool for the optimization of video signal processor architectures. ICASSP 1996: 1244-1247
Coauthor Index
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