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2020 – today
- 2022
[c5]Yen-Ting Tsou, Kuan-Hsun Chen
, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai:
This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator. ASP-DAC 2022: 702-707- 2021
- [c4]Chun-Yuan Huang, Der-Yu Tsai, Che-Rung Lee:
Memory hot-zone and its application to accelerate the convergence of KSM for VM consolidation. UCC Companion 2021: 23:1-23:6 - [c3]Samuel Liu, Jen-Ho Kuo, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, M.-H. Yang, Kai-Chiang Wu:
ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design. VLSI-DAT 2021: 1-7 - 2020
- [c2]Shu-Ming Liu, Luba Tang, Ning-Chi Huang, Der-Yu Tsai, Ming-Xue Yang, Kai-Chiang Wu:
Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator. VLSI-DAT 2020: 1-3
2010 – 2019
- 2019
- [c1]Wei-Fen Lin, Der-Yu Tsai, Luba Tang, Cheng-Tao Hsieh, Cheng-Yi Chou, Ping-Hao Chang, Luis Hsu:
ONNC: A Compilation Framework Connecting ONNX to Proprietary Deep Learning Accelerators. AICAS 2019: 214-218
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